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81106ddd1a
spapr now has the mechanism of constructing both XICS and XIVE instances of the SpaprInterruptController interface. However, only one of the interrupt controllers will actually be active at any given time, depending on feature negotiation with the guest. This is handled in the current code via spapr_irq_current() which checks the OV5 vector from feature negotiation to determine the current backend. Determining the active controller at the point we need it like this can be pretty confusing, because it makes it very non obvious at what points the active controller can change. This can make it difficult to reason about the code and where a change of active controller could appear in sequence with other events. Make this mechanism more explicit by adding an 'active_intc' pointer and an explicit spapr_irq_update_active_intc() function to update it from the CAS state. We also add hooks on the intc backend which will get called when it is activated or deactivated. For now we just introduce the switch and hooks, later patches will actually start using them. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Cédric Le Goater <clg@kaod.org>
107 lines
3.9 KiB
C
107 lines
3.9 KiB
C
/*
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* QEMU PowerPC sPAPR IRQ backend definitions
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*
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* Copyright (c) 2018, IBM Corporation.
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*
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* This code is licensed under the GPL version 2 or later. See the
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* COPYING file in the top-level directory.
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*/
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#ifndef HW_SPAPR_IRQ_H
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#define HW_SPAPR_IRQ_H
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#include "target/ppc/cpu-qom.h"
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/*
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* IRQ range offsets per device type
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*/
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#define SPAPR_IRQ_IPI 0x0
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#define SPAPR_XIRQ_BASE XICS_IRQ_BASE /* 0x1000 */
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#define SPAPR_IRQ_EPOW (SPAPR_XIRQ_BASE + 0x0000)
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#define SPAPR_IRQ_HOTPLUG (SPAPR_XIRQ_BASE + 0x0001)
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#define SPAPR_IRQ_VIO (SPAPR_XIRQ_BASE + 0x0100) /* 256 VIO devices */
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#define SPAPR_IRQ_PCI_LSI (SPAPR_XIRQ_BASE + 0x0200) /* 32+ PHBs devices */
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/* Offset of the dynamic range covered by the bitmap allocator */
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#define SPAPR_IRQ_MSI (SPAPR_XIRQ_BASE + 0x0300)
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#define SPAPR_NR_XIRQS 0x1000
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#define SPAPR_NR_MSIS (SPAPR_XIRQ_BASE + SPAPR_NR_XIRQS - SPAPR_IRQ_MSI)
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typedef struct SpaprMachineState SpaprMachineState;
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typedef struct SpaprInterruptController SpaprInterruptController;
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#define TYPE_SPAPR_INTC "spapr-interrupt-controller"
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#define SPAPR_INTC(obj) \
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INTERFACE_CHECK(SpaprInterruptController, (obj), TYPE_SPAPR_INTC)
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#define SPAPR_INTC_CLASS(klass) \
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OBJECT_CLASS_CHECK(SpaprInterruptControllerClass, (klass), TYPE_SPAPR_INTC)
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#define SPAPR_INTC_GET_CLASS(obj) \
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OBJECT_GET_CLASS(SpaprInterruptControllerClass, (obj), TYPE_SPAPR_INTC)
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typedef struct SpaprInterruptControllerClass {
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InterfaceClass parent;
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int (*activate)(SpaprInterruptController *intc, Error **errp);
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void (*deactivate)(SpaprInterruptController *intc);
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/*
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* These methods will typically be called on all intcs, active and
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* inactive
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*/
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int (*cpu_intc_create)(SpaprInterruptController *intc,
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PowerPCCPU *cpu, Error **errp);
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int (*claim_irq)(SpaprInterruptController *intc, int irq, bool lsi,
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Error **errp);
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void (*free_irq)(SpaprInterruptController *intc, int irq);
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} SpaprInterruptControllerClass;
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void spapr_irq_update_active_intc(SpaprMachineState *spapr);
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int spapr_irq_cpu_intc_create(SpaprMachineState *spapr,
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PowerPCCPU *cpu, Error **errp);
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void spapr_irq_msi_init(SpaprMachineState *spapr, uint32_t nr_msis);
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int spapr_irq_msi_alloc(SpaprMachineState *spapr, uint32_t num, bool align,
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Error **errp);
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void spapr_irq_msi_free(SpaprMachineState *spapr, int irq, uint32_t num);
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typedef struct SpaprIrq {
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uint32_t nr_xirqs;
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uint32_t nr_msis;
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bool xics;
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bool xive;
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void (*print_info)(SpaprMachineState *spapr, Monitor *mon);
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void (*dt_populate)(SpaprMachineState *spapr, uint32_t nr_servers,
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void *fdt, uint32_t phandle);
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int (*post_load)(SpaprMachineState *spapr, int version_id);
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void (*reset)(SpaprMachineState *spapr, Error **errp);
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void (*set_irq)(void *opaque, int srcno, int val);
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void (*init_kvm)(SpaprMachineState *spapr, Error **errp);
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} SpaprIrq;
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extern SpaprIrq spapr_irq_xics;
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extern SpaprIrq spapr_irq_xics_legacy;
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extern SpaprIrq spapr_irq_xive;
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extern SpaprIrq spapr_irq_dual;
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void spapr_irq_init(SpaprMachineState *spapr, Error **errp);
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int spapr_irq_claim(SpaprMachineState *spapr, int irq, bool lsi, Error **errp);
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void spapr_irq_free(SpaprMachineState *spapr, int irq, int num);
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qemu_irq spapr_qirq(SpaprMachineState *spapr, int irq);
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int spapr_irq_post_load(SpaprMachineState *spapr, int version_id);
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void spapr_irq_reset(SpaprMachineState *spapr, Error **errp);
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int spapr_irq_get_phandle(SpaprMachineState *spapr, void *fdt, Error **errp);
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/*
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* XICS legacy routines
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*/
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int spapr_irq_find(SpaprMachineState *spapr, int num, bool align, Error **errp);
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#define spapr_irq_findone(spapr, errp) spapr_irq_find(spapr, 1, false, errp)
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#endif
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