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a4b84608ba
This is an effort to clean up the hw/riscv directory. Ideally it should only contain the RISC-V SoC / machine codes plus generic codes. Let's move sifive_test model to hw/misc directory. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1599129623-68957-10-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
46 lines
1.2 KiB
C
46 lines
1.2 KiB
C
/*
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* QEMU Test Finisher interface
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*
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* Copyright (c) 2018 SiFive, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_SIFIVE_TEST_H
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#define HW_SIFIVE_TEST_H
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#include "hw/sysbus.h"
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#define TYPE_SIFIVE_TEST "riscv.sifive.test"
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#define SIFIVE_TEST(obj) \
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OBJECT_CHECK(SiFiveTestState, (obj), TYPE_SIFIVE_TEST)
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typedef struct SiFiveTestState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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MemoryRegion mmio;
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} SiFiveTestState;
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enum {
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FINISHER_FAIL = 0x3333,
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FINISHER_PASS = 0x5555,
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FINISHER_RESET = 0x7777
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};
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DeviceState *sifive_test_create(hwaddr addr);
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#endif
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