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Generated using: $ ./scripts/codeconverter/converter.py -i \ --pattern=TypeCheckMacro $(git grep -l '' -- '*.[ch]') Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Message-Id: <20200831210740.126168-12-ehabkost@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Message-Id: <20200831210740.126168-13-ehabkost@redhat.com> Message-Id: <20200831210740.126168-14-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
64 lines
1.8 KiB
C
64 lines
1.8 KiB
C
/*
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* Raspberry Pi emulation (c) 2012 Gregory Estrade
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* Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous
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*
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* Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft
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* Written by Andrew Baumann
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*
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* ARM Local Timer IRQ Copyright (c) 2019. Zoltán Baldaszti
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* Added basic IRQ_TIMER interrupt support
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#ifndef BCM2836_CONTROL_H
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#define BCM2836_CONTROL_H
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#include "hw/sysbus.h"
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#include "qemu/timer.h"
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#include "qom/object.h"
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/* 4 mailboxes per core, for 16 total */
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#define BCM2836_NCORES 4
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#define BCM2836_MBPERCORE 4
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#define TYPE_BCM2836_CONTROL "bcm2836-control"
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typedef struct BCM2836ControlState BCM2836ControlState;
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DECLARE_INSTANCE_CHECKER(BCM2836ControlState, BCM2836_CONTROL,
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TYPE_BCM2836_CONTROL)
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struct BCM2836ControlState {
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/*< private >*/
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SysBusDevice busdev;
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/*< public >*/
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MemoryRegion iomem;
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/* mailbox state */
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uint32_t mailboxes[BCM2836_NCORES * BCM2836_MBPERCORE];
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/* interrupt routing/control registers */
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uint8_t route_gpu_irq, route_gpu_fiq;
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uint32_t timercontrol[BCM2836_NCORES];
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uint32_t mailboxcontrol[BCM2836_NCORES];
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/* interrupt status regs (derived from input pins; not visible to user) */
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bool gpu_irq, gpu_fiq;
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uint8_t timerirqs[BCM2836_NCORES];
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/* local timer */
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QEMUTimer timer;
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uint32_t local_timer_control;
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uint8_t route_localtimer;
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/* interrupt source registers, post-routing (also input-derived; visible) */
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uint32_t irqsrc[BCM2836_NCORES];
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uint32_t fiqsrc[BCM2836_NCORES];
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/* outputs to CPU cores */
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qemu_irq irq[BCM2836_NCORES];
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qemu_irq fiq[BCM2836_NCORES];
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};
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#endif
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