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	 f7697f0e62
			
		
	
	
		f7697f0e62
		
	
	
	
	
		
			
			Add basic CPU state description to the newly created machine.c Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20201026115530.304-3-jiangyifei@huawei.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
		
			
				
	
	
		
			36 lines
		
	
	
		
			1.0 KiB
		
	
	
	
		
			Meson
		
	
	
	
	
	
			
		
		
	
	
			36 lines
		
	
	
		
			1.0 KiB
		
	
	
	
		
			Meson
		
	
	
	
	
	
| # FIXME extra_args should accept files()
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| dir = meson.current_source_dir()
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| gen32 = [
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|   decodetree.process('insn16.decode', extra_args: [dir / 'insn16-32.decode', '--static-decode=decode_insn16', '--insnwidth=16']),
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|   decodetree.process('insn32.decode', extra_args: '--static-decode=decode_insn32'),
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| ]
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| 
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| gen64 = [
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|   decodetree.process('insn16.decode', extra_args: [dir / 'insn16-64.decode', '--static-decode=decode_insn16', '--insnwidth=16']),
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|   decodetree.process('insn32.decode', extra_args: [dir / 'insn32-64.decode', '--static-decode=decode_insn32']),
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| ]
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| 
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| riscv_ss = ss.source_set()
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| riscv_ss.add(when: 'TARGET_RISCV32', if_true: gen32)
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| riscv_ss.add(when: 'TARGET_RISCV64', if_true: gen64)
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| riscv_ss.add(files(
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|   'cpu.c',
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|   'cpu_helper.c',
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|   'csr.c',
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|   'fpu_helper.c',
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|   'gdbstub.c',
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|   'op_helper.c',
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|   'vector_helper.c',
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|   'translate.c',
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| ))
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| 
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| riscv_softmmu_ss = ss.source_set()
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| riscv_softmmu_ss.add(files(
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|   'pmp.c',
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|   'monitor.c',
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|   'machine.c'
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| ))
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| 
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| target_arch += {'riscv': riscv_ss}
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| target_softmmu_arch += {'riscv': riscv_softmmu_ss}
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