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The RAS feature has a block of memory-mapped registers at offset 0x5000 within the PPB. For a "minimal RAS" implementation we provide no error records and so the only registers that exist in the block are ERRIIDR and ERRDEVID. The "RAZ/WI for privileged, BusFault for nonprivileged" behaviour of the "nvic-default" region is actually valid for minimal-RAS, so the main benefit of providing an explicit implementation of the register block is more accurate LOG_UNIMP messages, and a framework for where we could add a real RAS implementation later if necessary. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20201119215617.29887-27-peter.maydell@linaro.org
98 lines
3.1 KiB
C
98 lines
3.1 KiB
C
/*
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* ARMv7M NVIC object
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*
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* Copyright (c) 2017 Linaro Ltd
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* Written by Peter Maydell <peter.maydell@linaro.org>
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*
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* This code is licensed under the GPL version 2 or later.
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*/
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#ifndef HW_ARM_ARMV7M_NVIC_H
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#define HW_ARM_ARMV7M_NVIC_H
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#include "target/arm/cpu.h"
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#include "hw/sysbus.h"
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#include "hw/timer/armv7m_systick.h"
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#include "qom/object.h"
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#define TYPE_NVIC "armv7m_nvic"
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typedef struct NVICState NVICState;
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DECLARE_INSTANCE_CHECKER(NVICState, NVIC,
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TYPE_NVIC)
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/* Highest permitted number of exceptions (architectural limit) */
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#define NVIC_MAX_VECTORS 512
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/* Number of internal exceptions */
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#define NVIC_INTERNAL_VECTORS 16
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typedef struct VecInfo {
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/* Exception priorities can range from -3 to 255; only the unmodifiable
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* priority values for RESET, NMI and HardFault can be negative.
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*/
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int16_t prio;
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uint8_t enabled;
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uint8_t pending;
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uint8_t active;
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uint8_t level; /* exceptions <=15 never set level */
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} VecInfo;
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struct NVICState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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ARMCPU *cpu;
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VecInfo vectors[NVIC_MAX_VECTORS];
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/* If the v8M security extension is implemented, some of the internal
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* exceptions are banked between security states (ie there exists both
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* a Secure and a NonSecure version of the exception and its state):
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* HardFault, MemManage, UsageFault, SVCall, PendSV, SysTick (R_PJHV)
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* The rest (including all the external exceptions) are not banked, though
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* they may be configurable to target either Secure or NonSecure state.
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* We store the secure exception state in sec_vectors[] for the banked
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* exceptions, and otherwise use only vectors[] (including for exceptions
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* like SecureFault that unconditionally target Secure state).
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* Entries in sec_vectors[] for non-banked exception numbers are unused.
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*/
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VecInfo sec_vectors[NVIC_INTERNAL_VECTORS];
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/* The PRIGROUP field in AIRCR is banked */
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uint32_t prigroup[M_REG_NUM_BANKS];
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uint8_t num_prio_bits;
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/* v8M NVIC_ITNS state (stored as a bool per bit) */
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bool itns[NVIC_MAX_VECTORS];
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/* The following fields are all cached state that can be recalculated
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* from the vectors[] and sec_vectors[] arrays and the prigroup field:
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* - vectpending
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* - vectpending_is_secure
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* - exception_prio
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* - vectpending_prio
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*/
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unsigned int vectpending; /* highest prio pending enabled exception */
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/* true if vectpending is a banked secure exception, ie it is in
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* sec_vectors[] rather than vectors[]
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*/
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bool vectpending_is_s_banked;
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int exception_prio; /* group prio of the highest prio active exception */
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int vectpending_prio; /* group prio of the exeception in vectpending */
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MemoryRegion sysregmem;
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MemoryRegion sysreg_ns_mem;
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MemoryRegion systickmem;
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MemoryRegion systick_ns_mem;
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MemoryRegion ras_mem;
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MemoryRegion container;
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MemoryRegion defaultmem;
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uint32_t num_irq;
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qemu_irq excpout;
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qemu_irq sysresetreq;
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SysTickState systick[M_REG_NUM_BANKS];
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};
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#endif
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