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10fb1340b1
Since cpu_check_irqs() doesn't reference to anything outside of CPUSPARCState, it better belongs to the architectural code in target/, rather than the hardware specific code in hw/. Note: while we moved the trace events, we don't rename them. Remark: this allows us to build the leon3 machine stand alone, fixing this link failure (because cpu_check_irqs is defined in hw/sparc/sun4m.c which is only built when CONFIG_SUN4M is selected): /usr/bin/ld: target_sparc_win_helper.c.o: in function `cpu_put_psr': target/sparc/win_helper.c:91: undefined reference to `cpu_check_irqs' Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210428141655.387430-5-f4bug@amsat.org> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
305 lines
9.2 KiB
C
305 lines
9.2 KiB
C
/*
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* Sparc64 interrupt helpers
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/main-loop.h"
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#include "cpu.h"
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#include "exec/helper-proto.h"
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#include "exec/log.h"
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#include "trace.h"
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#define DEBUG_PCALL
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#ifdef DEBUG_PCALL
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static const char * const excp_names[0x80] = {
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[TT_TFAULT] = "Instruction Access Fault",
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[TT_TMISS] = "Instruction Access MMU Miss",
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[TT_CODE_ACCESS] = "Instruction Access Error",
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[TT_ILL_INSN] = "Illegal Instruction",
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[TT_PRIV_INSN] = "Privileged Instruction",
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[TT_NFPU_INSN] = "FPU Disabled",
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[TT_FP_EXCP] = "FPU Exception",
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[TT_TOVF] = "Tag Overflow",
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[TT_CLRWIN] = "Clean Windows",
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[TT_DIV_ZERO] = "Division By Zero",
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[TT_DFAULT] = "Data Access Fault",
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[TT_DMISS] = "Data Access MMU Miss",
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[TT_DATA_ACCESS] = "Data Access Error",
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[TT_DPROT] = "Data Protection Error",
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[TT_UNALIGNED] = "Unaligned Memory Access",
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[TT_PRIV_ACT] = "Privileged Action",
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[TT_EXTINT | 0x1] = "External Interrupt 1",
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[TT_EXTINT | 0x2] = "External Interrupt 2",
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[TT_EXTINT | 0x3] = "External Interrupt 3",
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[TT_EXTINT | 0x4] = "External Interrupt 4",
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[TT_EXTINT | 0x5] = "External Interrupt 5",
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[TT_EXTINT | 0x6] = "External Interrupt 6",
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[TT_EXTINT | 0x7] = "External Interrupt 7",
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[TT_EXTINT | 0x8] = "External Interrupt 8",
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[TT_EXTINT | 0x9] = "External Interrupt 9",
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[TT_EXTINT | 0xa] = "External Interrupt 10",
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[TT_EXTINT | 0xb] = "External Interrupt 11",
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[TT_EXTINT | 0xc] = "External Interrupt 12",
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[TT_EXTINT | 0xd] = "External Interrupt 13",
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[TT_EXTINT | 0xe] = "External Interrupt 14",
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[TT_EXTINT | 0xf] = "External Interrupt 15",
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};
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#endif
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void cpu_check_irqs(CPUSPARCState *env)
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{
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CPUState *cs;
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uint32_t pil = env->pil_in |
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(env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER));
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/* We should be holding the BQL before we mess with IRQs */
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g_assert(qemu_mutex_iothread_locked());
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/* TT_IVEC has a higher priority (16) than TT_EXTINT (31..17) */
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if (env->ivec_status & 0x20) {
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return;
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}
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cs = env_cpu(env);
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/*
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* check if TM or SM in SOFTINT are set
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* setting these also causes interrupt 14
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*/
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if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) {
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pil |= 1 << 14;
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}
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/*
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* The bit corresponding to psrpil is (1<< psrpil),
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* the next bit is (2 << psrpil).
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*/
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if (pil < (2 << env->psrpil)) {
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if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
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trace_sparc64_cpu_check_irqs_reset_irq(env->interrupt_index);
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env->interrupt_index = 0;
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cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
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}
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return;
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}
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if (cpu_interrupts_enabled(env)) {
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unsigned int i;
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for (i = 15; i > env->psrpil; i--) {
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if (pil & (1 << i)) {
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int old_interrupt = env->interrupt_index;
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int new_interrupt = TT_EXTINT | i;
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if (unlikely(env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt
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&& ((cpu_tsptr(env)->tt & 0x1f0) == TT_EXTINT))) {
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trace_sparc64_cpu_check_irqs_noset_irq(env->tl,
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cpu_tsptr(env)->tt,
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new_interrupt);
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} else if (old_interrupt != new_interrupt) {
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env->interrupt_index = new_interrupt;
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trace_sparc64_cpu_check_irqs_set_irq(i, old_interrupt,
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new_interrupt);
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cpu_interrupt(cs, CPU_INTERRUPT_HARD);
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}
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break;
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}
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}
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} else if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
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trace_sparc64_cpu_check_irqs_disabled(pil, env->pil_in, env->softint,
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env->interrupt_index);
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env->interrupt_index = 0;
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cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
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}
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}
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void sparc_cpu_do_interrupt(CPUState *cs)
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{
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SPARCCPU *cpu = SPARC_CPU(cs);
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CPUSPARCState *env = &cpu->env;
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int intno = cs->exception_index;
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trap_state *tsptr;
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/* Compute PSR before exposing state. */
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if (env->cc_op != CC_OP_FLAGS) {
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cpu_get_psr(env);
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}
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#ifdef DEBUG_PCALL
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if (qemu_loglevel_mask(CPU_LOG_INT)) {
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static int count;
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const char *name;
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if (intno < 0 || intno >= 0x1ff) {
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name = "Unknown";
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} else if (intno >= 0x180) {
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name = "Hyperprivileged Trap Instruction";
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} else if (intno >= 0x100) {
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name = "Trap Instruction";
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} else if (intno >= 0xc0) {
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name = "Window Fill";
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} else if (intno >= 0x80) {
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name = "Window Spill";
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} else {
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name = excp_names[intno];
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if (!name) {
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name = "Unknown";
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}
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}
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qemu_log("%6d: %s (v=%04x)\n", count, name, intno);
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log_cpu_state(cs, 0);
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#if 0
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{
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int i;
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uint8_t *ptr;
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qemu_log(" code=");
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ptr = (uint8_t *)env->pc;
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for (i = 0; i < 16; i++) {
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qemu_log(" %02x", ldub(ptr + i));
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}
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qemu_log("\n");
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}
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#endif
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count++;
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}
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#endif
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#if !defined(CONFIG_USER_ONLY)
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if (env->tl >= env->maxtl) {
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cpu_abort(cs, "Trap 0x%04x while trap level (%d) >= MAXTL (%d),"
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" Error state", cs->exception_index, env->tl, env->maxtl);
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return;
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}
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#endif
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if (env->tl < env->maxtl - 1) {
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env->tl++;
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} else {
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env->pstate |= PS_RED;
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if (env->tl < env->maxtl) {
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env->tl++;
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}
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}
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tsptr = cpu_tsptr(env);
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tsptr->tstate = sparc64_tstate(env);
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tsptr->tpc = env->pc;
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tsptr->tnpc = env->npc;
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tsptr->tt = intno;
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if (cpu_has_hypervisor(env)) {
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env->htstate[env->tl] = env->hpstate;
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/* XXX OpenSPARC T1 - UltraSPARC T3 have MAXPTL=2
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but this may change in the future */
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if (env->tl > 2) {
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env->hpstate |= HS_PRIV;
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}
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}
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if (env->def.features & CPU_FEATURE_GL) {
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cpu_gl_switch_gregs(env, env->gl + 1);
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env->gl++;
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}
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switch (intno) {
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case TT_IVEC:
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if (!cpu_has_hypervisor(env)) {
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cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_IG);
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}
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break;
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case TT_TFAULT:
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case TT_DFAULT:
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case TT_TMISS ... TT_TMISS + 3:
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case TT_DMISS ... TT_DMISS + 3:
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case TT_DPROT ... TT_DPROT + 3:
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if (cpu_has_hypervisor(env)) {
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env->hpstate |= HS_PRIV;
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env->pstate = PS_PEF | PS_PRIV;
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} else {
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cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_MG);
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}
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break;
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case TT_INSN_REAL_TRANSLATION_MISS ... TT_DATA_REAL_TRANSLATION_MISS:
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case TT_HTRAP ... TT_HTRAP + 127:
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env->hpstate |= HS_PRIV;
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break;
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default:
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cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_AG);
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break;
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}
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if (intno == TT_CLRWIN) {
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cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - 1));
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} else if ((intno & 0x1c0) == TT_SPILL) {
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cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - env->cansave - 2));
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} else if ((intno & 0x1c0) == TT_FILL) {
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cpu_set_cwp(env, cpu_cwp_inc(env, env->cwp + 1));
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}
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if (cpu_hypervisor_mode(env)) {
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env->pc = (env->htba & ~0x3fffULL) | (intno << 5);
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} else {
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env->pc = env->tbr & ~0x7fffULL;
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env->pc |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5);
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}
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env->npc = env->pc + 4;
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cs->exception_index = -1;
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}
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trap_state *cpu_tsptr(CPUSPARCState* env)
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{
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return &env->ts[env->tl & MAXTL_MASK];
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}
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static bool do_modify_softint(CPUSPARCState *env, uint32_t value)
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{
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if (env->softint != value) {
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env->softint = value;
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#if !defined(CONFIG_USER_ONLY)
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if (cpu_interrupts_enabled(env)) {
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qemu_mutex_lock_iothread();
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cpu_check_irqs(env);
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qemu_mutex_unlock_iothread();
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}
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#endif
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return true;
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}
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return false;
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}
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void helper_set_softint(CPUSPARCState *env, uint64_t value)
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{
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if (do_modify_softint(env, env->softint | (uint32_t)value)) {
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trace_int_helper_set_softint(env->softint);
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}
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}
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void helper_clear_softint(CPUSPARCState *env, uint64_t value)
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{
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if (do_modify_softint(env, env->softint & (uint32_t)~value)) {
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trace_int_helper_clear_softint(env->softint);
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}
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}
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void helper_write_softint(CPUSPARCState *env, uint64_t value)
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{
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if (do_modify_softint(env, (uint32_t)value)) {
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trace_int_helper_write_softint(env->softint);
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}
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}
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