mirror of
https://github.com/qemu/qemu.git
synced 2025-10-31 04:06:46 +00:00
cbff2db1e9
This patch realize the EIOINTC interrupt controller. Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-35-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
63 lines
2.4 KiB
C
63 lines
2.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
|
/*
|
|
* LoongArch 3A5000 ext interrupt controller definitions
|
|
*
|
|
* Copyright (C) 2021 Loongson Technology Corporation Limited
|
|
*/
|
|
|
|
#include "hw/sysbus.h"
|
|
#include "hw/loongarch/virt.h"
|
|
|
|
#ifndef LOONGARCH_EXTIOI_H
|
|
#define LOONGARCH_EXTIOI_H
|
|
|
|
#define LS3A_INTC_IP 8
|
|
#define EXTIOI_IRQS (256)
|
|
#define EXTIOI_IRQS_BITMAP_SIZE (256 / 8)
|
|
/* map to ipnum per 32 irqs */
|
|
#define EXTIOI_IRQS_IPMAP_SIZE (256 / 32)
|
|
#define EXTIOI_IRQS_COREMAP_SIZE 256
|
|
#define EXTIOI_IRQS_NODETYPE_COUNT 16
|
|
#define EXTIOI_IRQS_GROUP_COUNT 8
|
|
|
|
#define APIC_OFFSET 0x400
|
|
#define APIC_BASE (0x1000ULL + APIC_OFFSET)
|
|
|
|
#define EXTIOI_NODETYPE_START (0x4a0 - APIC_OFFSET)
|
|
#define EXTIOI_NODETYPE_END (0x4c0 - APIC_OFFSET)
|
|
#define EXTIOI_IPMAP_START (0x4c0 - APIC_OFFSET)
|
|
#define EXTIOI_IPMAP_END (0x4c8 - APIC_OFFSET)
|
|
#define EXTIOI_ENABLE_START (0x600 - APIC_OFFSET)
|
|
#define EXTIOI_ENABLE_END (0x620 - APIC_OFFSET)
|
|
#define EXTIOI_BOUNCE_START (0x680 - APIC_OFFSET)
|
|
#define EXTIOI_BOUNCE_END (0x6a0 - APIC_OFFSET)
|
|
#define EXTIOI_ISR_START (0x700 - APIC_OFFSET)
|
|
#define EXTIOI_ISR_END (0x720 - APIC_OFFSET)
|
|
#define EXTIOI_COREISR_START (0x800 - APIC_OFFSET)
|
|
#define EXTIOI_COREISR_END (0xB20 - APIC_OFFSET)
|
|
#define EXTIOI_COREMAP_START (0xC00 - APIC_OFFSET)
|
|
#define EXTIOI_COREMAP_END (0xD00 - APIC_OFFSET)
|
|
|
|
#define TYPE_LOONGARCH_EXTIOI "loongarch.extioi"
|
|
OBJECT_DECLARE_SIMPLE_TYPE(LoongArchExtIOI, LOONGARCH_EXTIOI)
|
|
struct LoongArchExtIOI {
|
|
SysBusDevice parent_obj;
|
|
/* hardware state */
|
|
uint32_t nodetype[EXTIOI_IRQS_NODETYPE_COUNT / 2];
|
|
uint32_t bounce[EXTIOI_IRQS_GROUP_COUNT];
|
|
uint32_t isr[EXTIOI_IRQS / 32];
|
|
uint32_t coreisr[LOONGARCH_MAX_VCPUS][EXTIOI_IRQS_GROUP_COUNT];
|
|
uint32_t enable[EXTIOI_IRQS / 32];
|
|
uint32_t ipmap[EXTIOI_IRQS_IPMAP_SIZE / 4];
|
|
uint32_t coremap[EXTIOI_IRQS / 4];
|
|
uint32_t sw_pending[EXTIOI_IRQS / 32];
|
|
DECLARE_BITMAP(sw_isr[LOONGARCH_MAX_VCPUS][LS3A_INTC_IP], EXTIOI_IRQS);
|
|
uint8_t sw_ipmap[EXTIOI_IRQS_IPMAP_SIZE];
|
|
uint8_t sw_coremap[EXTIOI_IRQS];
|
|
qemu_irq parent_irq[LOONGARCH_MAX_VCPUS][LS3A_INTC_IP];
|
|
qemu_irq irq[EXTIOI_IRQS];
|
|
MemoryRegion extioi_iocsr_mem[LOONGARCH_MAX_VCPUS];
|
|
MemoryRegion extioi_system_mem;
|
|
};
|
|
#endif /* LOONGARCH_EXTIOI_H */
|