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e178113ff6
Several QOM type names contain ',':
ARM,bitband-memory
etraxfs,pic
etraxfs,serial
etraxfs,timer
fsl,imx25
fsl,imx31
fsl,imx6
fsl,imx6ul
fsl,imx7
grlib,ahbpnp
grlib,apbpnp
grlib,apbuart
grlib,gptimer
grlib,irqmp
qemu,register
SUNW,bpp
SUNW,CS4231
SUNW,DBRI
SUNW,DBRI.prom
SUNW,fdtwo
SUNW,sx
SUNW,tcx
xilinx,zynq_slcr
xlnx,zynqmp
xlnx,zynqmp-pmu-soc
xlnx,zynq-xadc
These are all device types. They can't be plugged with -device /
device_add, except for xlnx,zynqmp-pmu-soc, and I doubt that one
actually works.
They *can* be used with -device / device_add to request help.
Usability is poor, though: you have to double the comma, like this:
$ qemu-system-x86_64 -device SUNW,,fdtwo,help
Trap for the unwary. The fact that this was broken in
device-introspect-test for more than six years until commit e27bd49876
fixed it demonstrates that "the unwary" includes seasoned developers.
One QOM type name contains ' ': "ICH9 SMB". Because having to
remember just one way to quote would be too easy.
Rename the "SUNW,FOO types to "sun-FOO". Summarily replace ',' and '
' by '-' in the other type names.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20210304140229.575481-2-armbru@redhat.com>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
129 lines
4.8 KiB
C
129 lines
4.8 KiB
C
/*
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* Freescale i.MX31 SoC emulation
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*
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* Copyright (C) 2015 Jean-Christophe Dubois <jcd@tribudubois.net>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#ifndef FSL_IMX31_H
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#define FSL_IMX31_H
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#include "hw/arm/boot.h"
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#include "hw/intc/imx_avic.h"
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#include "hw/misc/imx31_ccm.h"
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#include "hw/char/imx_serial.h"
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#include "hw/timer/imx_gpt.h"
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#include "hw/timer/imx_epit.h"
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#include "hw/i2c/imx_i2c.h"
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#include "hw/gpio/imx_gpio.h"
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#include "hw/watchdog/wdt_imx2.h"
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#include "exec/memory.h"
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#include "target/arm/cpu.h"
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#include "qom/object.h"
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#define TYPE_FSL_IMX31 "fsl-imx31"
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OBJECT_DECLARE_SIMPLE_TYPE(FslIMX31State, FSL_IMX31)
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#define FSL_IMX31_NUM_UARTS 2
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#define FSL_IMX31_NUM_EPITS 2
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#define FSL_IMX31_NUM_I2CS 3
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#define FSL_IMX31_NUM_GPIOS 3
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struct FslIMX31State {
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/*< private >*/
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DeviceState parent_obj;
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/*< public >*/
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ARMCPU cpu;
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IMXAVICState avic;
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IMX31CCMState ccm;
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IMXSerialState uart[FSL_IMX31_NUM_UARTS];
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IMXGPTState gpt;
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IMXEPITState epit[FSL_IMX31_NUM_EPITS];
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IMXI2CState i2c[FSL_IMX31_NUM_I2CS];
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IMXGPIOState gpio[FSL_IMX31_NUM_GPIOS];
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IMX2WdtState wdt;
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MemoryRegion secure_rom;
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MemoryRegion rom;
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MemoryRegion iram;
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MemoryRegion iram_alias;
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};
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#define FSL_IMX31_SECURE_ROM_ADDR 0x00000000
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#define FSL_IMX31_SECURE_ROM_SIZE 0x4000
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#define FSL_IMX31_ROM_ADDR 0x00404000
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#define FSL_IMX31_ROM_SIZE 0x4000
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#define FSL_IMX31_IRAM_ALIAS_ADDR 0x10000000
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#define FSL_IMX31_IRAM_ALIAS_SIZE 0xFFC0000
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#define FSL_IMX31_IRAM_ADDR 0x1FFFC000
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#define FSL_IMX31_IRAM_SIZE 0x4000
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#define FSL_IMX31_I2C1_ADDR 0x43F80000
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#define FSL_IMX31_I2C1_SIZE 0x4000
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#define FSL_IMX31_I2C3_ADDR 0x43F84000
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#define FSL_IMX31_I2C3_SIZE 0x4000
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#define FSL_IMX31_UART1_ADDR 0x43F90000
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#define FSL_IMX31_UART1_SIZE 0x4000
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#define FSL_IMX31_UART2_ADDR 0x43F94000
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#define FSL_IMX31_UART2_SIZE 0x4000
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#define FSL_IMX31_I2C2_ADDR 0x43F98000
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#define FSL_IMX31_I2C2_SIZE 0x4000
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#define FSL_IMX31_CCM_ADDR 0x53F80000
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#define FSL_IMX31_CCM_SIZE 0x4000
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#define FSL_IMX31_GPT_ADDR 0x53F90000
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#define FSL_IMX31_GPT_SIZE 0x4000
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#define FSL_IMX31_EPIT1_ADDR 0x53F94000
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#define FSL_IMX31_EPIT1_SIZE 0x4000
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#define FSL_IMX31_EPIT2_ADDR 0x53F98000
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#define FSL_IMX31_EPIT2_SIZE 0x4000
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#define FSL_IMX31_GPIO3_ADDR 0x53FA4000
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#define FSL_IMX31_GPIO3_SIZE 0x4000
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#define FSL_IMX31_GPIO1_ADDR 0x53FCC000
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#define FSL_IMX31_GPIO1_SIZE 0x4000
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#define FSL_IMX31_GPIO2_ADDR 0x53FD0000
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#define FSL_IMX31_GPIO2_SIZE 0x4000
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#define FSL_IMX31_WDT_ADDR 0x53FDC000
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#define FSL_IMX31_WDT_SIZE 0x4000
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#define FSL_IMX31_AVIC_ADDR 0x68000000
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#define FSL_IMX31_AVIC_SIZE 0x100
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#define FSL_IMX31_SDRAM0_ADDR 0x80000000
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#define FSL_IMX31_SDRAM0_SIZE 0x10000000
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#define FSL_IMX31_SDRAM1_ADDR 0x90000000
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#define FSL_IMX31_SDRAM1_SIZE 0x10000000
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#define FSL_IMX31_FLASH0_ADDR 0xA0000000
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#define FSL_IMX31_FLASH0_SIZE 0x8000000
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#define FSL_IMX31_FLASH1_ADDR 0xA8000000
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#define FSL_IMX31_FLASH1_SIZE 0x8000000
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#define FSL_IMX31_CS2_ADDR 0xB0000000
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#define FSL_IMX31_CS2_SIZE 0x2000000
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#define FSL_IMX31_CS3_ADDR 0xB2000000
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#define FSL_IMX31_CS3_SIZE 0x2000000
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#define FSL_IMX31_CS4_ADDR 0xB4000000
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#define FSL_IMX31_CS4_SIZE 0x2000000
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#define FSL_IMX31_CS5_ADDR 0xB6000000
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#define FSL_IMX31_CS5_SIZE 0x2000000
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#define FSL_IMX31_NAND_ADDR 0xB8000000
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#define FSL_IMX31_NAND_SIZE 0x1000
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#define FSL_IMX31_EPIT2_IRQ 27
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#define FSL_IMX31_EPIT1_IRQ 28
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#define FSL_IMX31_GPT_IRQ 29
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#define FSL_IMX31_UART2_IRQ 32
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#define FSL_IMX31_UART1_IRQ 45
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#define FSL_IMX31_I2C1_IRQ 10
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#define FSL_IMX31_I2C2_IRQ 4
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#define FSL_IMX31_I2C3_IRQ 3
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#define FSL_IMX31_GPIO1_IRQ 52
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#define FSL_IMX31_GPIO2_IRQ 51
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#define FSL_IMX31_GPIO3_IRQ 56
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#endif /* FSL_IMX31_H */
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