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d86d30192b
This adds just enough of a root port implementation to be able to enumerate root ports (creating the required DVSEC entries). What's not here yet is the MMIO nor the ability to write some of the DVSEC entries. This can be added with the qemu commandline by adding a rootport to a specific CXL host bridge. For example: -device cxl-rp,id=rp0,bus="cxl.0",addr=0.0,chassis=4 Like the host bridge patch, the ACPI tables aren't generated at this point and so system software cannot use it. Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20220429144110.25167-17-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
35 lines
588 B
Plaintext
35 lines
588 B
Plaintext
config PCIE_PORT
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bool
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default y if PCI_DEVICES
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depends on PCI_EXPRESS && MSI_NONBROKEN
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config PXB
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bool
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default y if Q35 || ARM_VIRT
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config XIO3130
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bool
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default y if PCI_DEVICES
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depends on PCI_EXPRESS && MSI_NONBROKEN
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config IOH3420
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bool
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default y if PCI_DEVICES
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depends on PCI_EXPRESS && MSI_NONBROKEN
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config I82801B11
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bool
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default y if PCI_DEVICES
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depends on PCI_EXPRESS
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config DEC_PCI
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bool
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config SIMBA
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bool
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config CXL
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bool
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default y if PCI_EXPRESS && PXB
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depends on PCI_EXPRESS && MSI_NONBROKEN && PXB
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