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			Add skeletal documentation for the highbank and midway machines. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210713142226.19155-4-peter.maydell@linaro.org
		
			
				
	
	
		
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			20 lines
		
	
	
		
			488 B
		
	
	
	
		
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| Calxeda Highbank and Midway (``highbank``, ``midway``)
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| ======================================================
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| 
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| ``highbank`` is a model of the Calxeda Highbank (ECX-1000) system,
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| which has four Cortex-A9 cores.
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| 
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| ``midway`` is a model of the Calxeda Midway (ECX-2000) system,
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| which has four Cortex-A15 cores.
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| 
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| Emulated devices:
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| 
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| - L2x0 cache controller
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| - SP804 dual timer
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| - PL011 UART
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| - PL061 GPIOs
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| - PL031 RTC
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| - PL022 synchronous serial port controller
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| - AHCI
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| - XGMAC ethernet controllers
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