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6027d27405
This patch adds irq number property for loongarch msi interrupt controller, and remove hard coding irq number macro. Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230104020518.2564263-2-zhaotianrui@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
51 lines
1.6 KiB
C
51 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* QEMU LoongArch CPU
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*
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* Copyright (c) 2021 Loongson Technology Corporation Limited
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*/
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#ifndef HW_LS7A_H
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#define HW_LS7A_H
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#include "hw/pci/pci.h"
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#include "hw/pci/pcie_host.h"
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#include "hw/pci-host/pam.h"
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#include "qemu/units.h"
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#include "qemu/range.h"
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#include "qom/object.h"
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#define VIRT_PCI_MEM_BASE 0x40000000UL
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#define VIRT_PCI_MEM_SIZE 0x40000000UL
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#define VIRT_PCI_IO_OFFSET 0x4000
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#define VIRT_PCI_CFG_BASE 0x20000000
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#define VIRT_PCI_CFG_SIZE 0x08000000
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#define VIRT_PCI_IO_BASE 0x18004000UL
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#define VIRT_PCI_IO_SIZE 0xC000
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#define VIRT_PCH_REG_BASE 0x10000000UL
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#define VIRT_IOAPIC_REG_BASE (VIRT_PCH_REG_BASE)
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#define VIRT_PCH_MSI_ADDR_LOW 0x2FF00000UL
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/*
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* According to the kernel pch irq start from 64 offset
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* 0 ~ 16 irqs used for non-pci device while 16 ~ 64 irqs
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* used for pci device.
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*/
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#define PCH_PIC_IRQ_OFFSET 64
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#define VIRT_DEVICE_IRQS 16
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#define VIRT_UART_IRQ (PCH_PIC_IRQ_OFFSET + 2)
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#define VIRT_UART_BASE 0x1fe001e0
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#define VIRT_UART_SIZE 0X100
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#define VIRT_RTC_IRQ (PCH_PIC_IRQ_OFFSET + 3)
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#define VIRT_MISC_REG_BASE (VIRT_PCH_REG_BASE + 0x00080000)
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#define VIRT_RTC_REG_BASE (VIRT_MISC_REG_BASE + 0x00050100)
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#define VIRT_RTC_LEN 0x100
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#define VIRT_SCI_IRQ (PCH_PIC_IRQ_OFFSET + 4)
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#define VIRT_PLATFORM_BUS_BASEADDRESS 0x16000000
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#define VIRT_PLATFORM_BUS_SIZE 0x2000000
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#define VIRT_PLATFORM_BUS_NUM_IRQS 2
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#define VIRT_PLATFORM_BUS_IRQ 69
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#endif
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