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458 lines
12 KiB
C
458 lines
12 KiB
C
/*
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* libqos PCI bindings
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*
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* Copyright IBM, Corp. 2012-2013
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*
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* Authors:
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* Anthony Liguori <aliguori@us.ibm.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "pci.h"
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#include "hw/pci/pci_regs.h"
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#include "qemu/host-utils.h"
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#include "qgraph.h"
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void qpci_device_foreach(QPCIBus *bus, int vendor_id, int device_id,
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void (*func)(QPCIDevice *dev, int devfn, void *data),
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void *data)
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{
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int slot;
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for (slot = 0; slot < 32; slot++) {
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int fn;
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for (fn = 0; fn < 8; fn++) {
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QPCIDevice *dev;
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dev = qpci_device_find(bus, QPCI_DEVFN(slot, fn));
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if (!dev) {
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continue;
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}
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if (vendor_id != -1 &&
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qpci_config_readw(dev, PCI_VENDOR_ID) != vendor_id) {
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g_free(dev);
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continue;
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}
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if (device_id != -1 &&
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qpci_config_readw(dev, PCI_DEVICE_ID) != device_id) {
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g_free(dev);
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continue;
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}
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func(dev, QPCI_DEVFN(slot, fn), data);
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}
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}
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}
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bool qpci_has_buggy_msi(QPCIDevice *dev)
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{
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return dev->bus->has_buggy_msi;
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}
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bool qpci_check_buggy_msi(QPCIDevice *dev)
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{
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if (qpci_has_buggy_msi(dev)) {
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g_test_skip("Skipping due to incomplete support for MSI");
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return true;
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}
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return false;
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}
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static void qpci_device_set(QPCIDevice *dev, QPCIBus *bus, int devfn)
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{
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g_assert(dev);
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dev->bus = bus;
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dev->devfn = devfn;
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}
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QPCIDevice *qpci_device_find(QPCIBus *bus, int devfn)
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{
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QPCIDevice *dev;
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dev = g_malloc0(sizeof(*dev));
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qpci_device_set(dev, bus, devfn);
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if (qpci_config_readw(dev, PCI_VENDOR_ID) == 0xFFFF) {
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g_free(dev);
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return NULL;
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}
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return dev;
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}
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void qpci_device_init(QPCIDevice *dev, QPCIBus *bus, QPCIAddress *addr)
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{
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uint16_t vendor_id, device_id;
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qpci_device_set(dev, bus, addr->devfn);
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vendor_id = qpci_config_readw(dev, PCI_VENDOR_ID);
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device_id = qpci_config_readw(dev, PCI_DEVICE_ID);
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g_assert(!addr->vendor_id || vendor_id == addr->vendor_id);
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g_assert(!addr->device_id || device_id == addr->device_id);
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}
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void qpci_device_enable(QPCIDevice *dev)
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{
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uint16_t cmd;
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/* FIXME -- does this need to be a bus callout? */
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cmd = qpci_config_readw(dev, PCI_COMMAND);
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cmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
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qpci_config_writew(dev, PCI_COMMAND, cmd);
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/* Verify the bits are now set. */
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cmd = qpci_config_readw(dev, PCI_COMMAND);
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g_assert_cmphex(cmd & PCI_COMMAND_IO, ==, PCI_COMMAND_IO);
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g_assert_cmphex(cmd & PCI_COMMAND_MEMORY, ==, PCI_COMMAND_MEMORY);
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g_assert_cmphex(cmd & PCI_COMMAND_MASTER, ==, PCI_COMMAND_MASTER);
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}
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/**
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* qpci_find_capability:
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* @dev: the PCI device
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* @id: the PCI Capability ID (PCI_CAP_ID_*)
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* @start_addr: 0 to begin iteration or the last return value to continue
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* iteration
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*
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* Iterate over the PCI Capabilities List.
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*
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* Returns: PCI Configuration Space offset of the capabililty structure or
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* 0 if no further matching capability is found
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*/
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uint8_t qpci_find_capability(QPCIDevice *dev, uint8_t id, uint8_t start_addr)
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{
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uint8_t cap;
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uint8_t addr;
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if (start_addr) {
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addr = qpci_config_readb(dev, start_addr + PCI_CAP_LIST_NEXT);
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} else {
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addr = qpci_config_readb(dev, PCI_CAPABILITY_LIST);
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}
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do {
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cap = qpci_config_readb(dev, addr);
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if (cap != id) {
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addr = qpci_config_readb(dev, addr + PCI_CAP_LIST_NEXT);
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}
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} while (cap != id && addr != 0);
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return addr;
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}
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void qpci_msix_enable(QPCIDevice *dev)
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{
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uint8_t addr;
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uint16_t val;
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uint32_t table;
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uint8_t bir_table;
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uint8_t bir_pba;
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addr = qpci_find_capability(dev, PCI_CAP_ID_MSIX, 0);
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g_assert_cmphex(addr, !=, 0);
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val = qpci_config_readw(dev, addr + PCI_MSIX_FLAGS);
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qpci_config_writew(dev, addr + PCI_MSIX_FLAGS, val | PCI_MSIX_FLAGS_ENABLE);
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table = qpci_config_readl(dev, addr + PCI_MSIX_TABLE);
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bir_table = table & PCI_MSIX_FLAGS_BIRMASK;
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dev->msix_table_bar = qpci_iomap(dev, bir_table, NULL);
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dev->msix_table_off = table & ~PCI_MSIX_FLAGS_BIRMASK;
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table = qpci_config_readl(dev, addr + PCI_MSIX_PBA);
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bir_pba = table & PCI_MSIX_FLAGS_BIRMASK;
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if (bir_pba != bir_table) {
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dev->msix_pba_bar = qpci_iomap(dev, bir_pba, NULL);
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} else {
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dev->msix_pba_bar = dev->msix_table_bar;
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}
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dev->msix_pba_off = table & ~PCI_MSIX_FLAGS_BIRMASK;
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dev->msix_enabled = true;
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}
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void qpci_msix_disable(QPCIDevice *dev)
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{
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uint8_t addr;
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uint16_t val;
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g_assert(dev->msix_enabled);
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addr = qpci_find_capability(dev, PCI_CAP_ID_MSIX, 0);
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g_assert_cmphex(addr, !=, 0);
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val = qpci_config_readw(dev, addr + PCI_MSIX_FLAGS);
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qpci_config_writew(dev, addr + PCI_MSIX_FLAGS,
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val & ~PCI_MSIX_FLAGS_ENABLE);
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if (dev->msix_pba_bar.addr != dev->msix_table_bar.addr) {
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qpci_iounmap(dev, dev->msix_pba_bar);
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}
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qpci_iounmap(dev, dev->msix_table_bar);
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dev->msix_enabled = 0;
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dev->msix_table_off = 0;
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dev->msix_pba_off = 0;
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}
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bool qpci_msix_pending(QPCIDevice *dev, uint16_t entry)
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{
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uint32_t pba_entry;
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uint8_t bit_n = entry % 32;
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uint64_t off = (entry / 32) * PCI_MSIX_ENTRY_SIZE / 4;
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g_assert(dev->msix_enabled);
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pba_entry = qpci_io_readl(dev, dev->msix_pba_bar, dev->msix_pba_off + off);
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qpci_io_writel(dev, dev->msix_pba_bar, dev->msix_pba_off + off,
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pba_entry & ~(1 << bit_n));
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return (pba_entry & (1 << bit_n)) != 0;
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}
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bool qpci_msix_masked(QPCIDevice *dev, uint16_t entry)
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{
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uint8_t addr;
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uint16_t val;
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uint64_t vector_off = dev->msix_table_off + entry * PCI_MSIX_ENTRY_SIZE;
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g_assert(dev->msix_enabled);
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addr = qpci_find_capability(dev, PCI_CAP_ID_MSIX, 0);
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g_assert_cmphex(addr, !=, 0);
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val = qpci_config_readw(dev, addr + PCI_MSIX_FLAGS);
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if (val & PCI_MSIX_FLAGS_MASKALL) {
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return true;
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} else {
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return (qpci_io_readl(dev, dev->msix_table_bar,
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vector_off + PCI_MSIX_ENTRY_VECTOR_CTRL)
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& PCI_MSIX_ENTRY_CTRL_MASKBIT) != 0;
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}
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}
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uint16_t qpci_msix_table_size(QPCIDevice *dev)
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{
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uint8_t addr;
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uint16_t control;
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addr = qpci_find_capability(dev, PCI_CAP_ID_MSIX, 0);
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g_assert_cmphex(addr, !=, 0);
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control = qpci_config_readw(dev, addr + PCI_MSIX_FLAGS);
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return (control & PCI_MSIX_FLAGS_QSIZE) + 1;
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}
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uint8_t qpci_config_readb(QPCIDevice *dev, uint8_t offset)
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{
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return dev->bus->config_readb(dev->bus, dev->devfn, offset);
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}
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uint16_t qpci_config_readw(QPCIDevice *dev, uint8_t offset)
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{
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return dev->bus->config_readw(dev->bus, dev->devfn, offset);
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}
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uint32_t qpci_config_readl(QPCIDevice *dev, uint8_t offset)
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{
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return dev->bus->config_readl(dev->bus, dev->devfn, offset);
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}
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void qpci_config_writeb(QPCIDevice *dev, uint8_t offset, uint8_t value)
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{
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dev->bus->config_writeb(dev->bus, dev->devfn, offset, value);
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}
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void qpci_config_writew(QPCIDevice *dev, uint8_t offset, uint16_t value)
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{
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dev->bus->config_writew(dev->bus, dev->devfn, offset, value);
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}
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void qpci_config_writel(QPCIDevice *dev, uint8_t offset, uint32_t value)
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{
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dev->bus->config_writel(dev->bus, dev->devfn, offset, value);
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}
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uint8_t qpci_io_readb(QPCIDevice *dev, QPCIBar token, uint64_t off)
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{
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if (token.addr < QPCI_PIO_LIMIT) {
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return dev->bus->pio_readb(dev->bus, token.addr + off);
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} else {
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uint8_t val;
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dev->bus->memread(dev->bus, token.addr + off, &val, sizeof(val));
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return val;
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}
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}
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uint16_t qpci_io_readw(QPCIDevice *dev, QPCIBar token, uint64_t off)
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{
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if (token.addr < QPCI_PIO_LIMIT) {
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return dev->bus->pio_readw(dev->bus, token.addr + off);
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} else {
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uint16_t val;
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dev->bus->memread(dev->bus, token.addr + off, &val, sizeof(val));
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return le16_to_cpu(val);
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}
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}
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uint32_t qpci_io_readl(QPCIDevice *dev, QPCIBar token, uint64_t off)
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{
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if (token.addr < QPCI_PIO_LIMIT) {
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return dev->bus->pio_readl(dev->bus, token.addr + off);
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} else {
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uint32_t val;
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dev->bus->memread(dev->bus, token.addr + off, &val, sizeof(val));
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return le32_to_cpu(val);
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}
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}
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uint64_t qpci_io_readq(QPCIDevice *dev, QPCIBar token, uint64_t off)
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{
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if (token.addr < QPCI_PIO_LIMIT) {
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return dev->bus->pio_readq(dev->bus, token.addr + off);
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} else {
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uint64_t val;
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dev->bus->memread(dev->bus, token.addr + off, &val, sizeof(val));
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return le64_to_cpu(val);
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}
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}
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void qpci_io_writeb(QPCIDevice *dev, QPCIBar token, uint64_t off,
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uint8_t value)
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{
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if (token.addr < QPCI_PIO_LIMIT) {
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dev->bus->pio_writeb(dev->bus, token.addr + off, value);
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} else {
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dev->bus->memwrite(dev->bus, token.addr + off, &value, sizeof(value));
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}
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}
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void qpci_io_writew(QPCIDevice *dev, QPCIBar token, uint64_t off,
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uint16_t value)
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{
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if (token.addr < QPCI_PIO_LIMIT) {
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dev->bus->pio_writew(dev->bus, token.addr + off, value);
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} else {
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value = cpu_to_le16(value);
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dev->bus->memwrite(dev->bus, token.addr + off, &value, sizeof(value));
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}
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}
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void qpci_io_writel(QPCIDevice *dev, QPCIBar token, uint64_t off,
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uint32_t value)
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{
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if (token.addr < QPCI_PIO_LIMIT) {
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dev->bus->pio_writel(dev->bus, token.addr + off, value);
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} else {
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value = cpu_to_le32(value);
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dev->bus->memwrite(dev->bus, token.addr + off, &value, sizeof(value));
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}
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}
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void qpci_io_writeq(QPCIDevice *dev, QPCIBar token, uint64_t off,
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uint64_t value)
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{
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if (token.addr < QPCI_PIO_LIMIT) {
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dev->bus->pio_writeq(dev->bus, token.addr + off, value);
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} else {
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value = cpu_to_le64(value);
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dev->bus->memwrite(dev->bus, token.addr + off, &value, sizeof(value));
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}
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}
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void qpci_memread(QPCIDevice *dev, QPCIBar token, uint64_t off,
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void *buf, size_t len)
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{
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g_assert(token.addr >= QPCI_PIO_LIMIT);
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dev->bus->memread(dev->bus, token.addr + off, buf, len);
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}
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void qpci_memwrite(QPCIDevice *dev, QPCIBar token, uint64_t off,
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const void *buf, size_t len)
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{
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g_assert(token.addr >= QPCI_PIO_LIMIT);
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dev->bus->memwrite(dev->bus, token.addr + off, buf, len);
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}
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QPCIBar qpci_iomap(QPCIDevice *dev, int barno, uint64_t *sizeptr)
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{
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QPCIBus *bus = dev->bus;
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static const int bar_reg_map[] = {
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PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_1, PCI_BASE_ADDRESS_2,
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PCI_BASE_ADDRESS_3, PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_5,
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};
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QPCIBar bar;
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int bar_reg;
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uint32_t addr, size;
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uint32_t io_type;
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uint64_t loc;
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g_assert(barno >= 0 && barno <= 5);
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bar_reg = bar_reg_map[barno];
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qpci_config_writel(dev, bar_reg, 0xFFFFFFFF);
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addr = qpci_config_readl(dev, bar_reg);
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io_type = addr & PCI_BASE_ADDRESS_SPACE;
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if (io_type == PCI_BASE_ADDRESS_SPACE_IO) {
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addr &= PCI_BASE_ADDRESS_IO_MASK;
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} else {
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addr &= PCI_BASE_ADDRESS_MEM_MASK;
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}
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g_assert(addr); /* Must have *some* size bits */
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size = 1U << ctz32(addr);
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if (sizeptr) {
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*sizeptr = size;
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}
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if (io_type == PCI_BASE_ADDRESS_SPACE_IO) {
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loc = QEMU_ALIGN_UP(bus->pio_alloc_ptr, size);
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g_assert(loc >= bus->pio_alloc_ptr);
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g_assert(loc + size <= QPCI_PIO_LIMIT); /* Keep PIO below 64kiB */
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bus->pio_alloc_ptr = loc + size;
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qpci_config_writel(dev, bar_reg, loc | PCI_BASE_ADDRESS_SPACE_IO);
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} else {
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loc = QEMU_ALIGN_UP(bus->mmio_alloc_ptr, size);
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/* Check for space */
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g_assert(loc >= bus->mmio_alloc_ptr);
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g_assert(loc + size <= bus->mmio_limit);
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bus->mmio_alloc_ptr = loc + size;
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qpci_config_writel(dev, bar_reg, loc);
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}
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bar.addr = loc;
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return bar;
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}
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void qpci_iounmap(QPCIDevice *dev, QPCIBar bar)
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{
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/* FIXME */
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}
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QPCIBar qpci_legacy_iomap(QPCIDevice *dev, uint16_t addr)
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{
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QPCIBar bar = { .addr = addr };
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return bar;
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}
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void add_qpci_address(QOSGraphEdgeOptions *opts, QPCIAddress *addr)
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{
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g_assert(addr);
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g_assert(opts);
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opts->arg = addr;
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opts->size_arg = sizeof(QPCIAddress);
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}
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