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31fa64ecfd
We must leave the 'int rwx' parameter to ppc_hash32_handle_mmu_fault for now, but will clean that up later. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210518201146.794854-5-richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
605 lines
18 KiB
C
605 lines
18 KiB
C
/*
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* PowerPC MMU, TLB and BAT emulation helpers for QEMU.
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*
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* Copyright (c) 2003-2007 Jocelyn Mayer
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* Copyright (c) 2013 David Gibson, IBM Corporation
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "exec/helper-proto.h"
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#include "sysemu/kvm.h"
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#include "kvm_ppc.h"
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#include "internal.h"
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#include "mmu-hash32.h"
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#include "exec/log.h"
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/* #define DEBUG_BAT */
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#ifdef DEBUG_BATS
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# define LOG_BATS(...) qemu_log_mask(CPU_LOG_MMU, __VA_ARGS__)
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#else
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# define LOG_BATS(...) do { } while (0)
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#endif
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struct mmu_ctx_hash32 {
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hwaddr raddr; /* Real address */
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int prot; /* Protection bits */
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int key; /* Access key */
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};
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static int ppc_hash32_pp_prot(int key, int pp, int nx)
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{
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int prot;
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if (key == 0) {
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switch (pp) {
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case 0x0:
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case 0x1:
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case 0x2:
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prot = PAGE_READ | PAGE_WRITE;
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break;
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case 0x3:
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prot = PAGE_READ;
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break;
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default:
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abort();
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}
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} else {
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switch (pp) {
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case 0x0:
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prot = 0;
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break;
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case 0x1:
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case 0x3:
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prot = PAGE_READ;
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break;
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case 0x2:
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prot = PAGE_READ | PAGE_WRITE;
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break;
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default:
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abort();
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}
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}
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if (nx == 0) {
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prot |= PAGE_EXEC;
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}
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return prot;
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}
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static int ppc_hash32_pte_prot(PowerPCCPU *cpu,
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target_ulong sr, ppc_hash_pte32_t pte)
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{
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CPUPPCState *env = &cpu->env;
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unsigned pp, key;
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key = !!(msr_pr ? (sr & SR32_KP) : (sr & SR32_KS));
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pp = pte.pte1 & HPTE32_R_PP;
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return ppc_hash32_pp_prot(key, pp, !!(sr & SR32_NX));
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}
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static target_ulong hash32_bat_size(PowerPCCPU *cpu,
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target_ulong batu, target_ulong batl)
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{
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CPUPPCState *env = &cpu->env;
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if ((msr_pr && !(batu & BATU32_VP))
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|| (!msr_pr && !(batu & BATU32_VS))) {
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return 0;
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}
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return BATU32_BEPI & ~((batu & BATU32_BL) << 15);
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}
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static int hash32_bat_prot(PowerPCCPU *cpu,
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target_ulong batu, target_ulong batl)
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{
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int pp, prot;
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prot = 0;
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pp = batl & BATL32_PP;
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if (pp != 0) {
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prot = PAGE_READ | PAGE_EXEC;
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if (pp == 0x2) {
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prot |= PAGE_WRITE;
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}
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}
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return prot;
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}
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static target_ulong hash32_bat_601_size(PowerPCCPU *cpu,
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target_ulong batu, target_ulong batl)
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{
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if (!(batl & BATL32_601_V)) {
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return 0;
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}
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return BATU32_BEPI & ~((batl & BATL32_601_BL) << 17);
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}
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static int hash32_bat_601_prot(PowerPCCPU *cpu,
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target_ulong batu, target_ulong batl)
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{
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CPUPPCState *env = &cpu->env;
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int key, pp;
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pp = batu & BATU32_601_PP;
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if (msr_pr == 0) {
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key = !!(batu & BATU32_601_KS);
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} else {
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key = !!(batu & BATU32_601_KP);
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}
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return ppc_hash32_pp_prot(key, pp, 0);
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}
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static hwaddr ppc_hash32_bat_lookup(PowerPCCPU *cpu, target_ulong ea,
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MMUAccessType access_type, int *prot)
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{
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CPUPPCState *env = &cpu->env;
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target_ulong *BATlt, *BATut;
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bool ifetch = access_type == MMU_INST_FETCH;
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int i;
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LOG_BATS("%s: %cBAT v " TARGET_FMT_lx "\n", __func__,
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ifetch ? 'I' : 'D', ea);
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if (ifetch) {
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BATlt = env->IBAT[1];
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BATut = env->IBAT[0];
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} else {
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BATlt = env->DBAT[1];
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BATut = env->DBAT[0];
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}
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for (i = 0; i < env->nb_BATs; i++) {
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target_ulong batu = BATut[i];
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target_ulong batl = BATlt[i];
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target_ulong mask;
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if (unlikely(env->mmu_model == POWERPC_MMU_601)) {
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mask = hash32_bat_601_size(cpu, batu, batl);
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} else {
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mask = hash32_bat_size(cpu, batu, batl);
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}
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LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx
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" BATl " TARGET_FMT_lx "\n", __func__,
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ifetch ? 'I' : 'D', i, ea, batu, batl);
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if (mask && ((ea & mask) == (batu & BATU32_BEPI))) {
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hwaddr raddr = (batl & mask) | (ea & ~mask);
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if (unlikely(env->mmu_model == POWERPC_MMU_601)) {
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*prot = hash32_bat_601_prot(cpu, batu, batl);
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} else {
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*prot = hash32_bat_prot(cpu, batu, batl);
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}
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return raddr & TARGET_PAGE_MASK;
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}
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}
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/* No hit */
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#if defined(DEBUG_BATS)
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if (qemu_log_enabled()) {
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LOG_BATS("no BAT match for " TARGET_FMT_lx ":\n", ea);
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for (i = 0; i < 4; i++) {
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BATu = &BATut[i];
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BATl = &BATlt[i];
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BEPIu = *BATu & BATU32_BEPIU;
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BEPIl = *BATu & BATU32_BEPIL;
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bl = (*BATu & 0x00001FFC) << 15;
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LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx
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" BATl " TARGET_FMT_lx "\n\t" TARGET_FMT_lx " "
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TARGET_FMT_lx " " TARGET_FMT_lx "\n",
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__func__, ifetch ? 'I' : 'D', i, ea,
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*BATu, *BATl, BEPIu, BEPIl, bl);
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}
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}
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#endif
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return -1;
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}
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static int ppc_hash32_direct_store(PowerPCCPU *cpu, target_ulong sr,
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target_ulong eaddr,
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MMUAccessType access_type,
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hwaddr *raddr, int *prot)
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{
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CPUState *cs = CPU(cpu);
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CPUPPCState *env = &cpu->env;
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int key = !!(msr_pr ? (sr & SR32_KP) : (sr & SR32_KS));
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qemu_log_mask(CPU_LOG_MMU, "direct store...\n");
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if ((sr & 0x1FF00000) >> 20 == 0x07f) {
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/*
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* Memory-forced I/O controller interface access
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*
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* If T=1 and BUID=x'07F', the 601 performs a memory access
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* to SR[28-31] LA[4-31], bypassing all protection mechanisms.
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*/
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*raddr = ((sr & 0xF) << 28) | (eaddr & 0x0FFFFFFF);
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*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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return 0;
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}
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if (access_type == MMU_INST_FETCH) {
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/* No code fetch is allowed in direct-store areas */
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cs->exception_index = POWERPC_EXCP_ISI;
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env->error_code = 0x10000000;
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return 1;
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}
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switch (env->access_type) {
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case ACCESS_INT:
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/* Integer load/store : only access allowed */
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break;
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case ACCESS_FLOAT:
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/* Floating point load/store */
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cs->exception_index = POWERPC_EXCP_ALIGN;
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env->error_code = POWERPC_EXCP_ALIGN_FP;
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env->spr[SPR_DAR] = eaddr;
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return 1;
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case ACCESS_RES:
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/* lwarx, ldarx or srwcx. */
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env->error_code = 0;
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env->spr[SPR_DAR] = eaddr;
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if (access_type == MMU_DATA_STORE) {
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env->spr[SPR_DSISR] = 0x06000000;
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} else {
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env->spr[SPR_DSISR] = 0x04000000;
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}
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return 1;
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case ACCESS_CACHE:
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/*
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* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi
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*
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* Should make the instruction do no-op. As it already do
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* no-op, it's quite easy :-)
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*/
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*raddr = eaddr;
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return 0;
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case ACCESS_EXT:
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/* eciwx or ecowx */
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cs->exception_index = POWERPC_EXCP_DSI;
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env->error_code = 0;
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env->spr[SPR_DAR] = eaddr;
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if (access_type == MMU_DATA_STORE) {
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env->spr[SPR_DSISR] = 0x06100000;
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} else {
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env->spr[SPR_DSISR] = 0x04100000;
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}
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return 1;
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default:
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cpu_abort(cs, "ERROR: instruction should not need "
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"address translation\n");
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}
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if ((access_type == MMU_DATA_STORE || key != 1) &&
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(access_type == MMU_DATA_LOAD || key != 0)) {
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*raddr = eaddr;
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return 0;
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} else {
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cs->exception_index = POWERPC_EXCP_DSI;
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env->error_code = 0;
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env->spr[SPR_DAR] = eaddr;
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if (access_type == MMU_DATA_STORE) {
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env->spr[SPR_DSISR] = 0x0a000000;
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} else {
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env->spr[SPR_DSISR] = 0x08000000;
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}
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return 1;
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}
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}
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hwaddr get_pteg_offset32(PowerPCCPU *cpu, hwaddr hash)
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{
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target_ulong mask = ppc_hash32_hpt_mask(cpu);
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return (hash * HASH_PTEG_SIZE_32) & mask;
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}
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static hwaddr ppc_hash32_pteg_search(PowerPCCPU *cpu, hwaddr pteg_off,
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bool secondary, target_ulong ptem,
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ppc_hash_pte32_t *pte)
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{
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hwaddr pte_offset = pteg_off;
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target_ulong pte0, pte1;
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int i;
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for (i = 0; i < HPTES_PER_GROUP; i++) {
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pte0 = ppc_hash32_load_hpte0(cpu, pte_offset);
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/*
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* pte0 contains the valid bit and must be read before pte1,
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* otherwise we might see an old pte1 with a new valid bit and
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* thus an inconsistent hpte value
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*/
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smp_rmb();
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pte1 = ppc_hash32_load_hpte1(cpu, pte_offset);
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if ((pte0 & HPTE32_V_VALID)
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&& (secondary == !!(pte0 & HPTE32_V_SECONDARY))
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&& HPTE32_V_COMPARE(pte0, ptem)) {
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pte->pte0 = pte0;
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pte->pte1 = pte1;
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return pte_offset;
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}
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pte_offset += HASH_PTE_SIZE_32;
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}
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return -1;
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}
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static void ppc_hash32_set_r(PowerPCCPU *cpu, hwaddr pte_offset, uint32_t pte1)
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{
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target_ulong base = ppc_hash32_hpt_base(cpu);
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hwaddr offset = pte_offset + 6;
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/* The HW performs a non-atomic byte update */
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stb_phys(CPU(cpu)->as, base + offset, ((pte1 >> 8) & 0xff) | 0x01);
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}
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static void ppc_hash32_set_c(PowerPCCPU *cpu, hwaddr pte_offset, uint64_t pte1)
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{
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target_ulong base = ppc_hash32_hpt_base(cpu);
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hwaddr offset = pte_offset + 7;
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/* The HW performs a non-atomic byte update */
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stb_phys(CPU(cpu)->as, base + offset, (pte1 & 0xff) | 0x80);
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}
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static hwaddr ppc_hash32_htab_lookup(PowerPCCPU *cpu,
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target_ulong sr, target_ulong eaddr,
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ppc_hash_pte32_t *pte)
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{
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hwaddr pteg_off, pte_offset;
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hwaddr hash;
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uint32_t vsid, pgidx, ptem;
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vsid = sr & SR32_VSID;
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pgidx = (eaddr & ~SEGMENT_MASK_256M) >> TARGET_PAGE_BITS;
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hash = vsid ^ pgidx;
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ptem = (vsid << 7) | (pgidx >> 10);
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/* Page address translation */
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qemu_log_mask(CPU_LOG_MMU, "htab_base " TARGET_FMT_plx
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" htab_mask " TARGET_FMT_plx
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" hash " TARGET_FMT_plx "\n",
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ppc_hash32_hpt_base(cpu), ppc_hash32_hpt_mask(cpu), hash);
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/* Primary PTEG lookup */
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qemu_log_mask(CPU_LOG_MMU, "0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
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" vsid=%" PRIx32 " ptem=%" PRIx32
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" hash=" TARGET_FMT_plx "\n",
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ppc_hash32_hpt_base(cpu), ppc_hash32_hpt_mask(cpu),
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vsid, ptem, hash);
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pteg_off = get_pteg_offset32(cpu, hash);
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pte_offset = ppc_hash32_pteg_search(cpu, pteg_off, 0, ptem, pte);
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if (pte_offset == -1) {
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/* Secondary PTEG lookup */
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qemu_log_mask(CPU_LOG_MMU, "1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
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" vsid=%" PRIx32 " api=%" PRIx32
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" hash=" TARGET_FMT_plx "\n", ppc_hash32_hpt_base(cpu),
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ppc_hash32_hpt_mask(cpu), vsid, ptem, ~hash);
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pteg_off = get_pteg_offset32(cpu, ~hash);
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pte_offset = ppc_hash32_pteg_search(cpu, pteg_off, 1, ptem, pte);
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}
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return pte_offset;
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}
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static hwaddr ppc_hash32_pte_raddr(target_ulong sr, ppc_hash_pte32_t pte,
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target_ulong eaddr)
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{
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hwaddr rpn = pte.pte1 & HPTE32_R_RPN;
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hwaddr mask = ~TARGET_PAGE_MASK;
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return (rpn & ~mask) | (eaddr & mask);
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}
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int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
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int mmu_idx)
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{
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CPUState *cs = CPU(cpu);
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CPUPPCState *env = &cpu->env;
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target_ulong sr;
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hwaddr pte_offset;
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ppc_hash_pte32_t pte;
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int prot;
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int need_prot;
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MMUAccessType access_type;
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hwaddr raddr;
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assert((rwx == 0) || (rwx == 1) || (rwx == 2));
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access_type = rwx;
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need_prot = prot_for_access_type(access_type);
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/* 1. Handle real mode accesses */
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if (access_type == MMU_INST_FETCH ? !msr_ir : !msr_dr) {
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/* Translation is off */
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raddr = eaddr;
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tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
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PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx,
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TARGET_PAGE_SIZE);
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return 0;
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}
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/* 2. Check Block Address Translation entries (BATs) */
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if (env->nb_BATs != 0) {
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raddr = ppc_hash32_bat_lookup(cpu, eaddr, access_type, &prot);
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if (raddr != -1) {
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if (need_prot & ~prot) {
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if (access_type == MMU_INST_FETCH) {
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cs->exception_index = POWERPC_EXCP_ISI;
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env->error_code = 0x08000000;
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} else {
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cs->exception_index = POWERPC_EXCP_DSI;
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env->error_code = 0;
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env->spr[SPR_DAR] = eaddr;
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if (access_type == MMU_DATA_STORE) {
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env->spr[SPR_DSISR] = 0x0a000000;
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} else {
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env->spr[SPR_DSISR] = 0x08000000;
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}
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}
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return 1;
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}
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tlb_set_page(cs, eaddr & TARGET_PAGE_MASK,
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raddr & TARGET_PAGE_MASK, prot, mmu_idx,
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TARGET_PAGE_SIZE);
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return 0;
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}
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}
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/* 3. Look up the Segment Register */
|
|
sr = env->sr[eaddr >> 28];
|
|
|
|
/* 4. Handle direct store segments */
|
|
if (sr & SR32_T) {
|
|
if (ppc_hash32_direct_store(cpu, sr, eaddr, access_type,
|
|
&raddr, &prot) == 0) {
|
|
tlb_set_page(cs, eaddr & TARGET_PAGE_MASK,
|
|
raddr & TARGET_PAGE_MASK, prot, mmu_idx,
|
|
TARGET_PAGE_SIZE);
|
|
return 0;
|
|
} else {
|
|
return 1;
|
|
}
|
|
}
|
|
|
|
/* 5. Check for segment level no-execute violation */
|
|
if (access_type == MMU_INST_FETCH && (sr & SR32_NX)) {
|
|
cs->exception_index = POWERPC_EXCP_ISI;
|
|
env->error_code = 0x10000000;
|
|
return 1;
|
|
}
|
|
|
|
/* 6. Locate the PTE in the hash table */
|
|
pte_offset = ppc_hash32_htab_lookup(cpu, sr, eaddr, &pte);
|
|
if (pte_offset == -1) {
|
|
if (access_type == MMU_INST_FETCH) {
|
|
cs->exception_index = POWERPC_EXCP_ISI;
|
|
env->error_code = 0x40000000;
|
|
} else {
|
|
cs->exception_index = POWERPC_EXCP_DSI;
|
|
env->error_code = 0;
|
|
env->spr[SPR_DAR] = eaddr;
|
|
if (access_type == MMU_DATA_STORE) {
|
|
env->spr[SPR_DSISR] = 0x42000000;
|
|
} else {
|
|
env->spr[SPR_DSISR] = 0x40000000;
|
|
}
|
|
}
|
|
|
|
return 1;
|
|
}
|
|
qemu_log_mask(CPU_LOG_MMU,
|
|
"found PTE at offset %08" HWADDR_PRIx "\n", pte_offset);
|
|
|
|
/* 7. Check access permissions */
|
|
|
|
prot = ppc_hash32_pte_prot(cpu, sr, pte);
|
|
|
|
if (need_prot & ~prot) {
|
|
/* Access right violation */
|
|
qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n");
|
|
if (access_type == MMU_INST_FETCH) {
|
|
cs->exception_index = POWERPC_EXCP_ISI;
|
|
env->error_code = 0x08000000;
|
|
} else {
|
|
cs->exception_index = POWERPC_EXCP_DSI;
|
|
env->error_code = 0;
|
|
env->spr[SPR_DAR] = eaddr;
|
|
if (access_type == MMU_DATA_STORE) {
|
|
env->spr[SPR_DSISR] = 0x0a000000;
|
|
} else {
|
|
env->spr[SPR_DSISR] = 0x08000000;
|
|
}
|
|
}
|
|
return 1;
|
|
}
|
|
|
|
qemu_log_mask(CPU_LOG_MMU, "PTE access granted !\n");
|
|
|
|
/* 8. Update PTE referenced and changed bits if necessary */
|
|
|
|
if (!(pte.pte1 & HPTE32_R_R)) {
|
|
ppc_hash32_set_r(cpu, pte_offset, pte.pte1);
|
|
}
|
|
if (!(pte.pte1 & HPTE32_R_C)) {
|
|
if (access_type == MMU_DATA_STORE) {
|
|
ppc_hash32_set_c(cpu, pte_offset, pte.pte1);
|
|
} else {
|
|
/*
|
|
* Treat the page as read-only for now, so that a later write
|
|
* will pass through this function again to set the C bit
|
|
*/
|
|
prot &= ~PAGE_WRITE;
|
|
}
|
|
}
|
|
|
|
/* 9. Determine the real address from the PTE */
|
|
|
|
raddr = ppc_hash32_pte_raddr(sr, pte, eaddr);
|
|
|
|
tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
|
|
prot, mmu_idx, TARGET_PAGE_SIZE);
|
|
|
|
return 0;
|
|
}
|
|
|
|
hwaddr ppc_hash32_get_phys_page_debug(PowerPCCPU *cpu, target_ulong eaddr)
|
|
{
|
|
CPUPPCState *env = &cpu->env;
|
|
target_ulong sr;
|
|
hwaddr pte_offset;
|
|
ppc_hash_pte32_t pte;
|
|
int prot;
|
|
|
|
if (msr_dr == 0) {
|
|
/* Translation is off */
|
|
return eaddr;
|
|
}
|
|
|
|
if (env->nb_BATs != 0) {
|
|
hwaddr raddr = ppc_hash32_bat_lookup(cpu, eaddr, 0, &prot);
|
|
if (raddr != -1) {
|
|
return raddr;
|
|
}
|
|
}
|
|
|
|
sr = env->sr[eaddr >> 28];
|
|
|
|
if (sr & SR32_T) {
|
|
/* FIXME: Add suitable debug support for Direct Store segments */
|
|
return -1;
|
|
}
|
|
|
|
pte_offset = ppc_hash32_htab_lookup(cpu, sr, eaddr, &pte);
|
|
if (pte_offset == -1) {
|
|
return -1;
|
|
}
|
|
|
|
return ppc_hash32_pte_raddr(sr, pte, eaddr) & TARGET_PAGE_MASK;
|
|
}
|