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5a28fa5ba1
This patch adds the GDB XML feature file that describes Alpha's core registers. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2569 Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Yodel Eldar <yodel.eldar@gmail.com> Message-ID: <20250630164124.26315-3-yodel.eldar@gmail.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-ID: <20250710104531.3099313-5-alex.bennee@linaro.org>
137 lines
5.8 KiB
XML
137 lines
5.8 KiB
XML
<?xml version="1.0"?>
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<!-- Copyright (C) 2025 Free Software Foundation, Inc.
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Copying and distribution of this file, with or without modification,
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are permitted in any medium without royalty provided the copyright
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notice and this notice are preserved. -->
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<!DOCTYPE feature SYSTEM "gdb-target.dtd">
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<feature name="org.gnu.gdb.alpha.core">
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<!-- IEEE rounding mode values -->
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<enum id="dyn_rm_enum" size="8">
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<!-- Chopped rounding mode -->
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<evalue name="chop" value="0"/>
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<!-- Minus infinity -->
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<evalue name="-inf" value="1"/>
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<!-- Normal rounding -->
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<evalue name="norm" value="2"/>
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<!-- Plus infinity -->
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<evalue name="+inf" value="3"/>
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</enum>
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<!-- Floating-Point Control Register Flags -->
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<flags id="fpcr_flags" size="8">
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<!-- Denormal Operand Exception Disable -->
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<field name="DNOD" start="47" end="47"/>
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<!-- Denormal Operands to Zero -->
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<field name="DNZ" start="48" end="48"/>
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<!-- Invalid Operation Disable -->
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<field name="INVD" start="49" end="49"/>
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<!-- Division by Zero Disable -->
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<field name="DZED" start="50" end="50"/>
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<!-- Overflow Disable -->
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<field name="OVFD" start="51" end="51"/>
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<!-- Invalid Operation -->
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<field name="INV" start="52" end="52"/>
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<!-- Division by Zero -->
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<field name="DZE" start="53" end="53"/>
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<!-- Overflow -->
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<field name="OVF" start="54" end="54"/>
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<!-- Underflow -->
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<field name="UNF" start="55" end="55"/>
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<!-- Inexact Result -->
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<field name="INE" start="56" end="56"/>
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<!-- Integer Overflow -->
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<field name="IOV" start="57" end="57"/>
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<!-- Dynamic Rounding Mode -->
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<field name="DYN_RM" start="58" end="59" type="dyn_rm_enum"/>
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<!-- Underflow to Zero -->
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<field name="UNDZ" start="60" end="60"/>
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<!-- Underflow Disable -->
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<field name="UNFD" start="61" end="61"/>
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<!-- Inexact Disable -->
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<field name="INED" start="62" end="62"/>
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<!-- Summary Bit -->
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<field name="SUM" start="63" end="63"/>
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</flags>
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<!-- Integer Registers -->
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<reg name="v0" bitsize="64" type="int64"/>
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<reg name="t0" bitsize="64" type="int64"/>
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<reg name="t1" bitsize="64" type="int64"/>
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<reg name="t2" bitsize="64" type="int64"/>
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<reg name="t3" bitsize="64" type="int64"/>
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<reg name="t4" bitsize="64" type="int64"/>
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<reg name="t5" bitsize="64" type="int64"/>
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<reg name="t6" bitsize="64" type="int64"/>
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<reg name="t7" bitsize="64" type="int64"/>
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<reg name="s0" bitsize="64" type="int64"/>
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<reg name="s1" bitsize="64" type="int64"/>
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<reg name="s2" bitsize="64" type="int64"/>
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<reg name="s3" bitsize="64" type="int64"/>
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<reg name="s4" bitsize="64" type="int64"/>
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<reg name="s5" bitsize="64" type="int64"/>
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<reg name="fp" bitsize="64" type="int64"/>
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<reg name="a0" bitsize="64" type="int64"/>
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<reg name="a1" bitsize="64" type="int64"/>
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<reg name="a2" bitsize="64" type="int64"/>
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<reg name="a3" bitsize="64" type="int64"/>
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<reg name="a4" bitsize="64" type="int64"/>
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<reg name="a5" bitsize="64" type="int64"/>
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<reg name="t8" bitsize="64" type="int64"/>
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<reg name="t9" bitsize="64" type="int64"/>
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<reg name="t10" bitsize="64" type="int64"/>
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<reg name="t11" bitsize="64" type="int64"/>
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<reg name="ra" bitsize="64" type="int64"/>
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<reg name="t12" bitsize="64" type="int64"/>
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<reg name="at" bitsize="64" type="int64"/>
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<reg name="gp" bitsize="64" type="data_ptr"/>
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<reg name="sp" bitsize="64" type="data_ptr"/>
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<reg name="zero" bitsize="64" type="int64" save-restore="no"/>
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<!-- Floating-Point Registers -->
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<reg name="f0" bitsize="64" type="float" group="float"/>
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<reg name="f1" bitsize="64" type="float" group="float"/>
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<reg name="f2" bitsize="64" type="float" group="float"/>
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<reg name="f3" bitsize="64" type="float" group="float"/>
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<reg name="f4" bitsize="64" type="float" group="float"/>
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<reg name="f5" bitsize="64" type="float" group="float"/>
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<reg name="f6" bitsize="64" type="float" group="float"/>
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<reg name="f7" bitsize="64" type="float" group="float"/>
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<reg name="f8" bitsize="64" type="float" group="float"/>
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<reg name="f9" bitsize="64" type="float" group="float"/>
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<reg name="f10" bitsize="64" type="float" group="float"/>
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<reg name="f11" bitsize="64" type="float" group="float"/>
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<reg name="f12" bitsize="64" type="float" group="float"/>
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<reg name="f13" bitsize="64" type="float" group="float"/>
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<reg name="f14" bitsize="64" type="float" group="float"/>
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<reg name="f15" bitsize="64" type="float" group="float"/>
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<reg name="f16" bitsize="64" type="float" group="float"/>
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<reg name="f17" bitsize="64" type="float" group="float"/>
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<reg name="f18" bitsize="64" type="float" group="float"/>
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<reg name="f19" bitsize="64" type="float" group="float"/>
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<reg name="f20" bitsize="64" type="float" group="float"/>
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<reg name="f21" bitsize="64" type="float" group="float"/>
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<reg name="f22" bitsize="64" type="float" group="float"/>
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<reg name="f23" bitsize="64" type="float" group="float"/>
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<reg name="f24" bitsize="64" type="float" group="float"/>
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<reg name="f25" bitsize="64" type="float" group="float"/>
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<reg name="f26" bitsize="64" type="float" group="float"/>
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<reg name="f27" bitsize="64" type="float" group="float"/>
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<reg name="f28" bitsize="64" type="float" group="float"/>
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<reg name="f29" bitsize="64" type="float" group="float"/>
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<reg name="f30" bitsize="64" type="float" group="float"/>
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<!-- Floating-Point Control Register -->
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<reg name="fpcr" bitsize="64" type="fpcr_flags" group="float"/>
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<!-- Program Counter -->
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<reg name="pc" bitsize="64" type="code_ptr"/>
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<!-- Reserved Index for Former Virtual Register -->
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<reg name="" bitsize="64" type="int64" save-restore="no"/>
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<!-- PALcode Memory Slot -->
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<reg name="unique" bitsize="64" type="int64" group="system"/>
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</feature>
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