Peter Maydell 51fd06e0ee hw/intc/arm_gic: Fix handling of GICC_APR<n>, GICC_NSAPR<n> registers ... A GICv2 has both GICC_APR<n> and GICC_NSAPR<n> registers, with the latter holding the active priority bits for Group 1 interrupts (usually Nonsecure interrupts), and the Nonsecure view of the GICC_APR<n> is the second half of the GICC_NSAPR<n> registers. Turn our half-hearted implementation of APR<n> into a proper implementation of both APR<n> and NSAPR<n>: * Add the underlying state for NSAPR<n> * Make sure APR<n> aren't visible for pre-GICv2 * Implement reading of NSAPR<n> * Make non-secure reads of APR<n> behave correctly * Implement writing to APR<n> and NSAPR<n> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1438089748-5528-4-git-send-email-peter.maydell@linaro.org		2015-09-08 17:38:42 +01:00
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allwinner-a10-pic.h	hw/intc: add allwinner A10 interrupt controller	2013-12-17 20:12:51 +00:00
arm_gic_common.h	hw/intc/arm_gic: Fix handling of GICC_APR<n>, GICC_NSAPR<n> registers	2015-09-08 17:38:42 +01:00
arm_gic.h	arm_gic: Extract headers hw/intc/arm_gic{,_common}.h	2013-11-05 17:47:29 +01:00
imx_avic.h	i.MX: Split AVIC emulator in a header file and a source file	2015-08-13 11:26:19 +01:00
realview_gic.h	realview_gic: Prepare for QOM embedding	2013-11-05 17:47:30 +01:00