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034c2e6902
Add a minimal model for the devcfg device which is part of Zynq. This model supports DMA capabilities and interrupt generation. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 83df49d8fa2d203a421ca71620809e4b04754e65.1467053537.git.alistair.francis@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
401 lines
14 KiB
C
401 lines
14 KiB
C
/*
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* QEMU model of the Xilinx Zynq Devcfg Interface
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*
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* (C) 2011 PetaLogix Pty Ltd
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* (C) 2014 Xilinx Inc.
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* Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "hw/dma/xlnx-zynq-devcfg.h"
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#include "qemu/bitops.h"
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#include "sysemu/sysemu.h"
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#include "sysemu/dma.h"
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#include "qemu/log.h"
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#define FREQ_HZ 900000000
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#define BTT_MAX 0x400
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#ifndef XLNX_ZYNQ_DEVCFG_ERR_DEBUG
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#define XLNX_ZYNQ_DEVCFG_ERR_DEBUG 0
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#endif
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#define DB_PRINT(fmt, args...) do { \
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if (XLNX_ZYNQ_DEVCFG_ERR_DEBUG) { \
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qemu_log("%s: " fmt, __func__, ## args); \
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} \
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} while (0);
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REG32(CTRL, 0x00)
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FIELD(CTRL, FORCE_RST, 31, 1) /* Not supported, wr ignored */
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FIELD(CTRL, PCAP_PR, 27, 1) /* Forced to 0 on bad unlock */
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FIELD(CTRL, PCAP_MODE, 26, 1)
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FIELD(CTRL, MULTIBOOT_EN, 24, 1)
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FIELD(CTRL, USER_MODE, 15, 1)
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FIELD(CTRL, PCFG_AES_FUSE, 12, 1)
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FIELD(CTRL, PCFG_AES_EN, 9, 3)
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FIELD(CTRL, SEU_EN, 8, 1)
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FIELD(CTRL, SEC_EN, 7, 1)
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FIELD(CTRL, SPNIDEN, 6, 1)
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FIELD(CTRL, SPIDEN, 5, 1)
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FIELD(CTRL, NIDEN, 4, 1)
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FIELD(CTRL, DBGEN, 3, 1)
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FIELD(CTRL, DAP_EN, 0, 3)
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REG32(LOCK, 0x04)
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#define AES_FUSE_LOCK 4
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#define AES_EN_LOCK 3
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#define SEU_LOCK 2
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#define SEC_LOCK 1
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#define DBG_LOCK 0
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/* mapping bits in R_LOCK to what they lock in R_CTRL */
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static const uint32_t lock_ctrl_map[] = {
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[AES_FUSE_LOCK] = R_CTRL_PCFG_AES_FUSE_MASK,
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[AES_EN_LOCK] = R_CTRL_PCFG_AES_EN_MASK,
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[SEU_LOCK] = R_CTRL_SEU_EN_MASK,
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[SEC_LOCK] = R_CTRL_SEC_EN_MASK,
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[DBG_LOCK] = R_CTRL_SPNIDEN_MASK | R_CTRL_SPIDEN_MASK |
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R_CTRL_NIDEN_MASK | R_CTRL_DBGEN_MASK |
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R_CTRL_DAP_EN_MASK,
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};
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REG32(CFG, 0x08)
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FIELD(CFG, RFIFO_TH, 10, 2)
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FIELD(CFG, WFIFO_TH, 8, 2)
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FIELD(CFG, RCLK_EDGE, 7, 1)
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FIELD(CFG, WCLK_EDGE, 6, 1)
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FIELD(CFG, DISABLE_SRC_INC, 5, 1)
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FIELD(CFG, DISABLE_DST_INC, 4, 1)
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#define R_CFG_RESET 0x50B
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REG32(INT_STS, 0x0C)
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FIELD(INT_STS, PSS_GTS_USR_B, 31, 1)
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FIELD(INT_STS, PSS_FST_CFG_B, 30, 1)
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FIELD(INT_STS, PSS_CFG_RESET_B, 27, 1)
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FIELD(INT_STS, RX_FIFO_OV, 18, 1)
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FIELD(INT_STS, WR_FIFO_LVL, 17, 1)
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FIELD(INT_STS, RD_FIFO_LVL, 16, 1)
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FIELD(INT_STS, DMA_CMD_ERR, 15, 1)
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FIELD(INT_STS, DMA_Q_OV, 14, 1)
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FIELD(INT_STS, DMA_DONE, 13, 1)
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FIELD(INT_STS, DMA_P_DONE, 12, 1)
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FIELD(INT_STS, P2D_LEN_ERR, 11, 1)
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FIELD(INT_STS, PCFG_DONE, 2, 1)
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#define R_INT_STS_RSVD ((0x7 << 24) | (0x1 << 19) | (0xF < 7))
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REG32(INT_MASK, 0x10)
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REG32(STATUS, 0x14)
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FIELD(STATUS, DMA_CMD_Q_F, 31, 1)
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FIELD(STATUS, DMA_CMD_Q_E, 30, 1)
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FIELD(STATUS, DMA_DONE_CNT, 28, 2)
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FIELD(STATUS, RX_FIFO_LVL, 20, 5)
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FIELD(STATUS, TX_FIFO_LVL, 12, 7)
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FIELD(STATUS, PSS_GTS_USR_B, 11, 1)
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FIELD(STATUS, PSS_FST_CFG_B, 10, 1)
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FIELD(STATUS, PSS_CFG_RESET_B, 5, 1)
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REG32(DMA_SRC_ADDR, 0x18)
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REG32(DMA_DST_ADDR, 0x1C)
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REG32(DMA_SRC_LEN, 0x20)
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REG32(DMA_DST_LEN, 0x24)
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REG32(ROM_SHADOW, 0x28)
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REG32(SW_ID, 0x30)
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REG32(UNLOCK, 0x34)
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#define R_UNLOCK_MAGIC 0x757BDF0D
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REG32(MCTRL, 0x80)
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FIELD(MCTRL, PS_VERSION, 28, 4)
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FIELD(MCTRL, PCFG_POR_B, 8, 1)
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FIELD(MCTRL, INT_PCAP_LPBK, 4, 1)
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FIELD(MCTRL, QEMU, 3, 1)
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static void xlnx_zynq_devcfg_update_ixr(XlnxZynqDevcfg *s)
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{
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qemu_set_irq(s->irq, ~s->regs[R_INT_MASK] & s->regs[R_INT_STS]);
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}
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static void xlnx_zynq_devcfg_reset(DeviceState *dev)
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{
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XlnxZynqDevcfg *s = XLNX_ZYNQ_DEVCFG(dev);
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int i;
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for (i = 0; i < XLNX_ZYNQ_DEVCFG_R_MAX; ++i) {
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register_reset(&s->regs_info[i]);
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}
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}
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static void xlnx_zynq_devcfg_dma_go(XlnxZynqDevcfg *s)
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{
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do {
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uint8_t buf[BTT_MAX];
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XlnxZynqDevcfgDMACmd *dmah = s->dma_cmd_fifo;
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uint32_t btt = BTT_MAX;
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bool loopback = s->regs[R_MCTRL] & R_MCTRL_INT_PCAP_LPBK_MASK;
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btt = MIN(btt, dmah->src_len);
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if (loopback) {
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btt = MIN(btt, dmah->dest_len);
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}
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DB_PRINT("reading %x bytes from %x\n", btt, dmah->src_addr);
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dma_memory_read(&address_space_memory, dmah->src_addr, buf, btt);
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dmah->src_len -= btt;
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dmah->src_addr += btt;
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if (loopback && (dmah->src_len || dmah->dest_len)) {
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DB_PRINT("writing %x bytes from %x\n", btt, dmah->dest_addr);
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dma_memory_write(&address_space_memory, dmah->dest_addr, buf, btt);
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dmah->dest_len -= btt;
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dmah->dest_addr += btt;
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}
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if (!dmah->src_len && !dmah->dest_len) {
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DB_PRINT("dma operation finished\n");
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s->regs[R_INT_STS] |= R_INT_STS_DMA_DONE_MASK |
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R_INT_STS_DMA_P_DONE_MASK;
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s->dma_cmd_fifo_num--;
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memmove(s->dma_cmd_fifo, &s->dma_cmd_fifo[1],
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sizeof(s->dma_cmd_fifo) - sizeof(s->dma_cmd_fifo[0]));
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}
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xlnx_zynq_devcfg_update_ixr(s);
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} while (s->dma_cmd_fifo_num);
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}
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static void r_ixr_post_write(RegisterInfo *reg, uint64_t val)
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{
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XlnxZynqDevcfg *s = XLNX_ZYNQ_DEVCFG(reg->opaque);
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xlnx_zynq_devcfg_update_ixr(s);
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}
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static uint64_t r_ctrl_pre_write(RegisterInfo *reg, uint64_t val)
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{
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XlnxZynqDevcfg *s = XLNX_ZYNQ_DEVCFG(reg->opaque);
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int i;
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for (i = 0; i < ARRAY_SIZE(lock_ctrl_map); ++i) {
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if (s->regs[R_LOCK] & 1 << i) {
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val &= ~lock_ctrl_map[i];
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val |= lock_ctrl_map[i] & s->regs[R_CTRL];
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}
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}
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return val;
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}
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static void r_ctrl_post_write(RegisterInfo *reg, uint64_t val)
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{
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const char *device_prefix = object_get_typename(OBJECT(reg->opaque));
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uint32_t aes_en = FIELD_EX32(val, CTRL, PCFG_AES_EN);
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if (aes_en != 0 && aes_en != 7) {
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qemu_log_mask(LOG_UNIMP, "%s: warning, aes-en bits inconsistent,"
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"unimplemented security reset should happen!\n",
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device_prefix);
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}
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}
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static void r_unlock_post_write(RegisterInfo *reg, uint64_t val)
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{
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XlnxZynqDevcfg *s = XLNX_ZYNQ_DEVCFG(reg->opaque);
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const char *device_prefix = object_get_typename(OBJECT(s));
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if (val == R_UNLOCK_MAGIC) {
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DB_PRINT("successful unlock\n");
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s->regs[R_CTRL] |= R_CTRL_PCAP_PR_MASK;
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s->regs[R_CTRL] |= R_CTRL_PCFG_AES_EN_MASK;
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memory_region_set_enabled(&s->iomem, true);
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} else { /* bad unlock attempt */
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qemu_log_mask(LOG_GUEST_ERROR, "%s: failed unlock\n", device_prefix);
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s->regs[R_CTRL] &= ~R_CTRL_PCAP_PR_MASK;
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s->regs[R_CTRL] &= ~R_CTRL_PCFG_AES_EN_MASK;
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/* core becomes inaccessible */
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memory_region_set_enabled(&s->iomem, false);
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}
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}
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static uint64_t r_lock_pre_write(RegisterInfo *reg, uint64_t val)
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{
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XlnxZynqDevcfg *s = XLNX_ZYNQ_DEVCFG(reg->opaque);
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/* once bits are locked they stay locked */
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return s->regs[R_LOCK] | val;
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}
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static void r_dma_dst_len_post_write(RegisterInfo *reg, uint64_t val)
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{
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XlnxZynqDevcfg *s = XLNX_ZYNQ_DEVCFG(reg->opaque);
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s->dma_cmd_fifo[s->dma_cmd_fifo_num] = (XlnxZynqDevcfgDMACmd) {
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.src_addr = s->regs[R_DMA_SRC_ADDR] & ~0x3UL,
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.dest_addr = s->regs[R_DMA_DST_ADDR] & ~0x3UL,
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.src_len = s->regs[R_DMA_SRC_LEN] << 2,
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.dest_len = s->regs[R_DMA_DST_LEN] << 2,
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};
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s->dma_cmd_fifo_num++;
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DB_PRINT("dma transfer started; %d total transfers pending\n",
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s->dma_cmd_fifo_num);
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xlnx_zynq_devcfg_dma_go(s);
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}
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static const RegisterAccessInfo xlnx_zynq_devcfg_regs_info[] = {
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{ .name = "CTRL", .addr = A_CTRL,
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.reset = R_CTRL_PCAP_PR_MASK | R_CTRL_PCAP_MODE_MASK | 0x3 << 13,
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.rsvd = 0x1 << 28 | 0x3ff << 13 | 0x3 << 13,
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.pre_write = r_ctrl_pre_write,
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.post_write = r_ctrl_post_write,
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},
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{ .name = "LOCK", .addr = A_LOCK,
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.rsvd = MAKE_64BIT_MASK(5, 64 - 5),
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.pre_write = r_lock_pre_write,
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},
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{ .name = "CFG", .addr = A_CFG,
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.reset = R_CFG_RESET,
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.rsvd = 0xfffff00f,
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},
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{ .name = "INT_STS", .addr = A_INT_STS,
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.w1c = ~R_INT_STS_RSVD,
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.reset = R_INT_STS_PSS_GTS_USR_B_MASK |
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R_INT_STS_PSS_CFG_RESET_B_MASK |
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R_INT_STS_WR_FIFO_LVL_MASK,
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.rsvd = R_INT_STS_RSVD,
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.post_write = r_ixr_post_write,
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},
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{ .name = "INT_MASK", .addr = A_INT_MASK,
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.reset = ~0,
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.rsvd = R_INT_STS_RSVD,
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.post_write = r_ixr_post_write,
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},
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{ .name = "STATUS", .addr = A_STATUS,
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.reset = R_STATUS_DMA_CMD_Q_E_MASK |
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R_STATUS_PSS_GTS_USR_B_MASK |
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R_STATUS_PSS_CFG_RESET_B_MASK,
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.ro = ~0,
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},
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{ .name = "DMA_SRC_ADDR", .addr = A_DMA_SRC_ADDR, },
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{ .name = "DMA_DST_ADDR", .addr = A_DMA_DST_ADDR, },
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{ .name = "DMA_SRC_LEN", .addr = A_DMA_SRC_LEN,
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.ro = MAKE_64BIT_MASK(27, 64 - 27) },
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{ .name = "DMA_DST_LEN", .addr = A_DMA_DST_LEN,
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.ro = MAKE_64BIT_MASK(27, 64 - 27),
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.post_write = r_dma_dst_len_post_write,
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},
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{ .name = "ROM_SHADOW", .addr = A_ROM_SHADOW,
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.rsvd = ~0ull,
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},
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{ .name = "SW_ID", .addr = A_SW_ID, },
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{ .name = "UNLOCK", .addr = A_UNLOCK,
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.post_write = r_unlock_post_write,
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},
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{ .name = "MCTRL", .addr = R_MCTRL * 4,
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/* Silicon 3.0 for version field, the mysterious reserved bit 23
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* and QEMU platform identifier.
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*/
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.reset = 0x2 << R_MCTRL_PS_VERSION_SHIFT | 1 << 23 | R_MCTRL_QEMU_MASK,
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.ro = ~R_MCTRL_INT_PCAP_LPBK_MASK,
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.rsvd = 0x00f00303,
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},
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};
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static const MemoryRegionOps xlnx_zynq_devcfg_reg_ops = {
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.read = register_read_memory,
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.write = register_write_memory,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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}
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};
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static const VMStateDescription vmstate_xlnx_zynq_devcfg_dma_cmd = {
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.name = "xlnx_zynq_devcfg_dma_cmd",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(src_addr, XlnxZynqDevcfgDMACmd),
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VMSTATE_UINT32(dest_addr, XlnxZynqDevcfgDMACmd),
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VMSTATE_UINT32(src_len, XlnxZynqDevcfgDMACmd),
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VMSTATE_UINT32(dest_len, XlnxZynqDevcfgDMACmd),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_xlnx_zynq_devcfg = {
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.name = "xlnx_zynq_devcfg",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_STRUCT_ARRAY(dma_cmd_fifo, XlnxZynqDevcfg,
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XLNX_ZYNQ_DEVCFG_DMA_CMD_FIFO_LEN, 0,
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vmstate_xlnx_zynq_devcfg_dma_cmd,
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XlnxZynqDevcfgDMACmd),
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VMSTATE_UINT8(dma_cmd_fifo_num, XlnxZynqDevcfg),
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VMSTATE_UINT32_ARRAY(regs, XlnxZynqDevcfg, XLNX_ZYNQ_DEVCFG_R_MAX),
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VMSTATE_END_OF_LIST()
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}
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};
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static void xlnx_zynq_devcfg_init(Object *obj)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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XlnxZynqDevcfg *s = XLNX_ZYNQ_DEVCFG(obj);
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RegisterInfoArray *reg_array;
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sysbus_init_irq(sbd, &s->irq);
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memory_region_init(&s->iomem, obj, "devcfg", XLNX_ZYNQ_DEVCFG_R_MAX * 4);
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reg_array =
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register_init_block32(DEVICE(obj), xlnx_zynq_devcfg_regs_info,
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ARRAY_SIZE(xlnx_zynq_devcfg_regs_info),
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s->regs_info, s->regs,
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&xlnx_zynq_devcfg_reg_ops,
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XLNX_ZYNQ_DEVCFG_ERR_DEBUG,
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XLNX_ZYNQ_DEVCFG_R_MAX);
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memory_region_add_subregion(&s->iomem,
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A_CTRL,
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®_array->mem);
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sysbus_init_mmio(sbd, &s->iomem);
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}
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static void xlnx_zynq_devcfg_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->reset = xlnx_zynq_devcfg_reset;
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dc->vmsd = &vmstate_xlnx_zynq_devcfg;
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}
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static const TypeInfo xlnx_zynq_devcfg_info = {
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.name = TYPE_XLNX_ZYNQ_DEVCFG,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(XlnxZynqDevcfg),
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.instance_init = xlnx_zynq_devcfg_init,
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.class_init = xlnx_zynq_devcfg_class_init,
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};
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static void xlnx_zynq_devcfg_register_types(void)
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{
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type_register_static(&xlnx_zynq_devcfg_info);
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}
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type_init(xlnx_zynq_devcfg_register_types)
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