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5747c0733d
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3672 c046a42c-6fe2-441c-8c8c-71466251a162
132 lines
4.6 KiB
C
132 lines
4.6 KiB
C
/*
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* MIPS emulation micro-operations templates for floating point reg
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* load & store for qemu.
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*
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* Copyright (c) 2006 Marius Groeger
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#if defined(FREG)
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#define OP_WLOAD_FREG(treg, tregname, FREG) \
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void glue(glue(op_load_fpr_,tregname), FREG) (void) \
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{ \
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treg = env->fpu->fpr[FREG].w[FP_ENDIAN_IDX]; \
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FORCE_RET(); \
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}
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#define OP_WSTORE_FREG(treg, tregname, FREG) \
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void glue(glue(op_store_fpr_,tregname), FREG) (void) \
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{ \
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env->fpu->fpr[FREG].w[FP_ENDIAN_IDX] = treg; \
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FORCE_RET(); \
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}
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/* WT0 = FREG.w: op_load_fpr_WT0_fprFREG */
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OP_WLOAD_FREG(WT0, WT0_fpr, FREG)
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/* FREG.w = WT0: op_store_fpr_WT0_fprFREG */
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OP_WSTORE_FREG(WT0, WT0_fpr, FREG)
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OP_WLOAD_FREG(WT1, WT1_fpr, FREG)
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OP_WSTORE_FREG(WT1, WT1_fpr, FREG)
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OP_WLOAD_FREG(WT2, WT2_fpr, FREG)
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OP_WSTORE_FREG(WT2, WT2_fpr, FREG)
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#define OP_DLOAD_FREG(treg, tregname, FREG) \
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void glue(glue(op_load_fpr_,tregname), FREG) (void) \
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{ \
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if (env->hflags & MIPS_HFLAG_F64) \
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treg = env->fpu->fpr[FREG].d; \
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else \
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treg = (uint64_t)(env->fpu->fpr[FREG | 1].w[FP_ENDIAN_IDX]) << 32 | \
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env->fpu->fpr[FREG & ~1].w[FP_ENDIAN_IDX]; \
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FORCE_RET(); \
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}
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#define OP_DSTORE_FREG(treg, tregname, FREG) \
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void glue(glue(op_store_fpr_,tregname), FREG) (void) \
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{ \
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if (env->hflags & MIPS_HFLAG_F64) \
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env->fpu->fpr[FREG].d = treg; \
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else { \
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env->fpu->fpr[FREG | 1].w[FP_ENDIAN_IDX] = treg >> 32; \
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env->fpu->fpr[FREG & ~1].w[FP_ENDIAN_IDX] = treg; \
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} \
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FORCE_RET(); \
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}
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OP_DLOAD_FREG(DT0, DT0_fpr, FREG)
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OP_DSTORE_FREG(DT0, DT0_fpr, FREG)
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OP_DLOAD_FREG(DT1, DT1_fpr, FREG)
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OP_DSTORE_FREG(DT1, DT1_fpr, FREG)
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OP_DLOAD_FREG(DT2, DT2_fpr, FREG)
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OP_DSTORE_FREG(DT2, DT2_fpr, FREG)
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#define OP_PSLOAD_FREG(treg, tregname, FREG) \
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void glue(glue(op_load_fpr_,tregname), FREG) (void) \
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{ \
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treg = env->fpu->fpr[FREG].w[!FP_ENDIAN_IDX]; \
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FORCE_RET(); \
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}
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#define OP_PSSTORE_FREG(treg, tregname, FREG) \
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void glue(glue(op_store_fpr_,tregname), FREG) (void) \
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{ \
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env->fpu->fpr[FREG].w[!FP_ENDIAN_IDX] = treg; \
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FORCE_RET(); \
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}
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OP_PSLOAD_FREG(WTH0, WTH0_fpr, FREG)
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OP_PSSTORE_FREG(WTH0, WTH0_fpr, FREG)
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OP_PSLOAD_FREG(WTH1, WTH1_fpr, FREG)
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OP_PSSTORE_FREG(WTH1, WTH1_fpr, FREG)
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OP_PSLOAD_FREG(WTH2, WTH2_fpr, FREG)
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OP_PSSTORE_FREG(WTH2, WTH2_fpr, FREG)
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#endif
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#if defined (FTN)
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#define SET_RESET(treg, tregname) \
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void glue(op_set, tregname)(void) \
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{ \
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treg = PARAM1; \
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FORCE_RET(); \
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} \
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void glue(op_reset, tregname)(void) \
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{ \
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treg = 0; \
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FORCE_RET(); \
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}
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SET_RESET(WT0, _WT0)
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SET_RESET(WT1, _WT1)
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SET_RESET(WT2, _WT2)
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SET_RESET(DT0, _DT0)
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SET_RESET(DT1, _DT1)
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SET_RESET(DT2, _DT2)
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SET_RESET(WTH0, _WTH0)
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SET_RESET(WTH1, _WTH1)
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SET_RESET(WTH2, _WTH2)
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#undef SET_RESET
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#endif
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