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b0fb84236d
When Linux reboots an e500 VM, it writes to a magic register in the "global-utilities" device indicated by the device tree. We were not emulating that device so far, rendering the VM reboot-less. This patch implements that device with only the reboot functionality implemented and adds it to the device tree. With this patch applied, I can successfully reboot a -M mpc8544ds VM. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Andreas Färber <andreas.faerber@web.de>
136 lines
3.7 KiB
C
136 lines
3.7 KiB
C
/*
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* QEMU PowerPC MPC8544 global util pseudo-device
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*
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* Copyright (C) 2011 Freescale Semiconductor, Inc. All rights reserved.
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*
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* Author: Alexander Graf, <alex@csgraf.de>
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*
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* This is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* *****************************************************************
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*
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* The documentation for this device is noted in the MPC8544 documentation,
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* file name "MPC8544ERM.pdf". You can easily find it on the web.
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*
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*/
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#include "hw.h"
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#include "sysemu.h"
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#include "sysbus.h"
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#define MPC8544_GUTS_MMIO_SIZE 0x1000
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#define MPC8544_GUTS_RSTCR_RESET 0x02
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#define MPC8544_GUTS_ADDR_PORPLLSR 0x00
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#define MPC8544_GUTS_ADDR_PORBMSR 0x04
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#define MPC8544_GUTS_ADDR_PORIMPSCR 0x08
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#define MPC8544_GUTS_ADDR_PORDEVSR 0x0C
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#define MPC8544_GUTS_ADDR_PORDBGMSR 0x10
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#define MPC8544_GUTS_ADDR_PORDEVSR2 0x14
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#define MPC8544_GUTS_ADDR_GPPORCR 0x20
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#define MPC8544_GUTS_ADDR_GPIOCR 0x30
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#define MPC8544_GUTS_ADDR_GPOUTDR 0x40
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#define MPC8544_GUTS_ADDR_GPINDR 0x50
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#define MPC8544_GUTS_ADDR_PMUXCR 0x60
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#define MPC8544_GUTS_ADDR_DEVDISR 0x70
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#define MPC8544_GUTS_ADDR_POWMGTCSR 0x80
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#define MPC8544_GUTS_ADDR_MCPSUMR 0x90
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#define MPC8544_GUTS_ADDR_RSTRSCR 0x94
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#define MPC8544_GUTS_ADDR_PVR 0xA0
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#define MPC8544_GUTS_ADDR_SVR 0xA4
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#define MPC8544_GUTS_ADDR_RSTCR 0xB0
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#define MPC8544_GUTS_ADDR_IOVSELSR 0xC0
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#define MPC8544_GUTS_ADDR_DDRCSR 0xB20
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#define MPC8544_GUTS_ADDR_DDRCDR 0xB24
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#define MPC8544_GUTS_ADDR_DDRCLKDR 0xB28
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#define MPC8544_GUTS_ADDR_CLKOCR 0xE00
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#define MPC8544_GUTS_ADDR_SRDS1CR1 0xF04
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#define MPC8544_GUTS_ADDR_SRDS2CR1 0xF10
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#define MPC8544_GUTS_ADDR_SRDS2CR3 0xF18
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struct GutsState {
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SysBusDevice busdev;
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};
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typedef struct GutsState GutsState;
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static uint32_t mpc8544_guts_read32(void *opaque, target_phys_addr_t addr)
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{
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uint32_t value = 0;
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CPUState *env = cpu_single_env;
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addr &= MPC8544_GUTS_MMIO_SIZE - 1;
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switch (addr) {
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case MPC8544_GUTS_ADDR_PVR:
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value = env->spr[SPR_PVR];
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break;
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case MPC8544_GUTS_ADDR_SVR:
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value = env->spr[SPR_E500_SVR];
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break;
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default:
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fprintf(stderr, "guts: Unknown register read: %x\n", (int)addr);
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break;
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}
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return value;
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}
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static CPUReadMemoryFunc * const mpc8544_guts_read[] = {
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NULL,
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NULL,
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&mpc8544_guts_read32,
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};
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static void mpc8544_guts_write32(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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addr &= MPC8544_GUTS_MMIO_SIZE - 1;
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switch (addr) {
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case MPC8544_GUTS_ADDR_RSTCR:
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if (value & MPC8544_GUTS_RSTCR_RESET) {
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qemu_system_reset_request();
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}
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break;
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default:
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fprintf(stderr, "guts: Unknown register write: %x = %x\n",
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(int)addr, value);
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break;
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}
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}
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static CPUWriteMemoryFunc * const mpc8544_guts_write[] = {
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NULL,
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NULL,
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&mpc8544_guts_write32,
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};
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static int mpc8544_guts_initfn(SysBusDevice *dev)
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{
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GutsState *s;
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int iomem;
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s = FROM_SYSBUS(GutsState, sysbus_from_qdev(dev));
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iomem = cpu_register_io_memory(mpc8544_guts_read, mpc8544_guts_write, s,
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DEVICE_BIG_ENDIAN);
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sysbus_init_mmio(dev, MPC8544_GUTS_MMIO_SIZE, iomem);
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return 0;
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}
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static SysBusDeviceInfo mpc8544_guts_info = {
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.init = mpc8544_guts_initfn,
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.qdev.name = "mpc8544-guts",
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.qdev.size = sizeof(GutsState),
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};
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static void mpc8544_guts_register(void)
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{
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sysbus_register_withprop(&mpc8544_guts_info);
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}
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device_init(mpc8544_guts_register);
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