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4bade28288
This tag contains a handful of patches that I'd like to target for 4.1: * An emulation for SiFive's GPIO device. * A fix to disallow sfence.vma from userspace. * Additional decodetree cleanups that should have no functional impact. * C extension emulation fidelity fixes that were noticed as part of that cleanup process. * A new "spike" target, along with the deprecation of a handful of old targets and CPUs. * Some initial infastructure related to the hypervisor extension. * An emulation fidelity fix that prevents prevents arbitrary bits in the SIP CSR from being set. * A small performance improvement that avoids excessive TLB flushing when the ASID does not change. This time I've used a new testing workflow: I've tested on both 32-bit and 64-bit builds of OpenEmbedded, via the default OpenSBI-based boot flow. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEAM520YNJYN/OiG3470yhUCzLq0EFAlzohuUTHHBhbG1lckBk YWJiZWx0LmNvbQAKCRDvTKFQLMurQfcKD/9xSyQld3g41e4qrcq/MHHQhIou0Mpj FdJ9jb5k8ndlhJix1RCJorXQ4ld7KPco5ywdQGebEzrSlsI0hanlWkrtBDibR9dU OoNjrBRqKAjTQOkIsmgQMW961n9HnfSZNlmm/L1n94TC/6W4/g+hlvDXQNJjyDKX u8QalbfNFlolSv11vOxSlVFTo8Cb6/++yBitvbLdNnquWcDgxid6FYWKMEmYB4jK pOTzlb0ZDdvS7rGLdMkTB2pTqrvEykP1uLvXpF7qOurGgoeHul2lqKiRuVcFFU46 6IOsaiwzDtMoUHzuFZypEJfnm0uJ4FEGEK8ZQBXlQhl2c0MDLXzXhIekKZIs/BmG K1Anio30zgfJscA6Zv6ZPataeEbPQ/l0LeAgS/Q8n7zIN5oRi3D9kdNTlo1MoSpD RLXESf0uXaTxkOAiyQ2hDj/NuPqja4TFD6UKj91eoWIhcga8i4olqsvLmsTsxhCK aaaiLGpYnmm/yhmBjMOAeBnu03w0ApTFS2UoPoMvTnrhZI4OXhm9XABEASpzdh57 5mJL/U8eJ098QSxBui2Sjcpn8mxfy1FHqAQl+urDCAb6/P/94+729LVzyuvEV08U IHYMFjO8v4e56Sf6eys6rcPYpPV/jrLnyL8uFODN1PsXY9+OyH/KLCGVb1vyAgsP nhE2uPKTnIrPqA== =7LvI -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.1-sf0' into staging RISC-V Patches for the 4.1 Soft Freeze, Part 1 This tag contains a handful of patches that I'd like to target for 4.1: * An emulation for SiFive's GPIO device. * A fix to disallow sfence.vma from userspace. * Additional decodetree cleanups that should have no functional impact. * C extension emulation fidelity fixes that were noticed as part of that cleanup process. * A new "spike" target, along with the deprecation of a handful of old targets and CPUs. * Some initial infastructure related to the hypervisor extension. * An emulation fidelity fix that prevents prevents arbitrary bits in the SIP CSR from being set. * A small performance improvement that avoids excessive TLB flushing when the ASID does not change. This time I've used a new testing workflow: I've tested on both 32-bit and 64-bit builds of OpenEmbedded, via the default OpenSBI-based boot flow. # gpg: Signature made Sat 25 May 2019 01:05:57 BST # gpg: using RSA key 00CE76D1834960DFCE886DF8EF4CA1502CCBAB41 # gpg: issuer "palmer@dabbelt.com" # gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>" [unknown] # gpg: aka "Palmer Dabbelt <palmer@sifive.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 00CE 76D1 8349 60DF CE88 6DF8 EF4C A150 2CCB AB41 * remotes/palmer/tags/riscv-for-master-4.1-sf0: (29 commits) target/riscv: Only flush TLB if SATP.ASID changes target/riscv: More accurate handling of `sip` CSR target/riscv: Add checks for several RVC reserved operands target/riscv: Add the HGATP register masks target/riscv: Add the HSTATUS register masks target/riscv: Add Hypervisor CSR macros target/riscv: Allow setting mstatus virtulisation bits target/riscv: Add the MPV and MTL mstatus bits target/riscv: Improve the scause logic target/riscv: Trigger interrupt on MIP update asynchronously target/riscv: Mark privilege level 2 as reserved riscv: spike: Add a generic spike machine target/riscv: Deprecate the generic no MMU CPUs target/riscv: Add a base 32 and 64 bit CPU target/riscv: Create settable CPU properties riscv: virt: Allow specifying a CPU via commandline linux-user/riscv: Add the CPU type as a comment target/riscv: Remove unused include of riscv_htif.h for virt board riscv target/riscv: Remove spaces from register names target/riscv: Split gen_arith_imm into functional and temp ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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| .. | ||
| acpi | ||
| adc | ||
| arm | ||
| audio | ||
| block | ||
| char | ||
| core | ||
| cpu | ||
| cris | ||
| display | ||
| dma | ||
| firmware | ||
| gpio | ||
| hyperv | ||
| i2c | ||
| i386 | ||
| ide | ||
| input | ||
| intc | ||
| ipack | ||
| ipmi | ||
| isa | ||
| kvm | ||
| lm32 | ||
| m68k | ||
| mem | ||
| mips | ||
| misc | ||
| net | ||
| nvram | ||
| pci | ||
| pci-bridge | ||
| pci-host | ||
| ppc | ||
| rdma | ||
| riscv | ||
| s390x | ||
| scsi | ||
| sd | ||
| sh4 | ||
| sparc | ||
| ssi | ||
| timer | ||
| tricore | ||
| unicore32 | ||
| usb | ||
| vfio | ||
| virtio | ||
| watchdog | ||
| xen | ||
| xtensa | ||
| boards.h | ||
| bt.h | ||
| elf_ops.h | ||
| empty_slot.h | ||
| fw-path-provider.h | ||
| hotplug.h | ||
| hw.h | ||
| ide.h | ||
| irq.h | ||
| loader-fit.h | ||
| loader.h | ||
| nmi.h | ||
| or-irq.h | ||
| pcmcia.h | ||
| platform-bus.h | ||
| ptimer.h | ||
| qdev-core.h | ||
| qdev-dma.h | ||
| qdev-properties.h | ||
| qdev.h | ||
| register.h | ||
| registerfields.h | ||
| stream.h | ||
| sysbus.h | ||
| usb.h | ||