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The SSE-200 has a CPU_IDENTITY register block, which is a set of read-only registers. As well as the usual PID/CID registers, there is a single CPUID register which indicates whether the CPU is CPU 0 or CPU 1. Implement a model of this register block. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-20-peter.maydell@linaro.org
42 lines
1.1 KiB
C
42 lines
1.1 KiB
C
/*
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* ARM SSE-200 CPU_IDENTITY register block
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*
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* Copyright (c) 2019 Linaro Limited
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* Written by Peter Maydell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 or
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* (at your option) any later version.
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*/
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/*
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* This is a model of the "CPU_IDENTITY" register block which is part of the
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* Arm SSE-200 and documented in
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* http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf
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*
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* QEMU interface:
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* + QOM property "CPUID": the value to use for the CPUID register
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* + sysbus MMIO region 0: the system information register bank
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*/
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#ifndef HW_MISC_ARMSSE_CPUID_H
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#define HW_MISC_ARMSSE_CPUID_H
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#include "hw/sysbus.h"
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#define TYPE_ARMSSE_CPUID "armsse-cpuid"
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#define ARMSSE_CPUID(obj) OBJECT_CHECK(ARMSSECPUID, (obj), TYPE_ARMSSE_CPUID)
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typedef struct ARMSSECPUID {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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MemoryRegion iomem;
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/* Properties */
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uint32_t cpuid;
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} ARMSSECPUID;
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#endif
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