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b91a0fa70c
Add asm-riscv/kvm.h for RISC-V KVM. Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> Signed-off-by: Mingwang Li <limingwang@huawei.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Message-id: 20220112081329.1835-2-jiangyifei@huawei.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
129 lines
3.3 KiB
C
129 lines
3.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
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/*
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* Copyright (C) 2019 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Anup Patel <anup.patel@wdc.com>
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*/
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#ifndef __LINUX_KVM_RISCV_H
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#define __LINUX_KVM_RISCV_H
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#ifndef __ASSEMBLY__
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#include <linux/types.h>
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#include <asm/ptrace.h>
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#define __KVM_HAVE_READONLY_MEM
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#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
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#define KVM_INTERRUPT_SET -1U
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#define KVM_INTERRUPT_UNSET -2U
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/* for KVM_GET_REGS and KVM_SET_REGS */
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struct kvm_regs {
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};
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/* for KVM_GET_FPU and KVM_SET_FPU */
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struct kvm_fpu {
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};
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/* KVM Debug exit structure */
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struct kvm_debug_exit_arch {
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};
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/* for KVM_SET_GUEST_DEBUG */
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struct kvm_guest_debug_arch {
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};
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/* definition of registers in kvm_run */
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struct kvm_sync_regs {
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};
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/* for KVM_GET_SREGS and KVM_SET_SREGS */
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struct kvm_sregs {
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};
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/* CONFIG registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
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struct kvm_riscv_config {
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unsigned long isa;
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};
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/* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
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struct kvm_riscv_core {
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struct user_regs_struct regs;
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unsigned long mode;
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};
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/* Possible privilege modes for kvm_riscv_core */
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#define KVM_RISCV_MODE_S 1
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#define KVM_RISCV_MODE_U 0
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/* CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
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struct kvm_riscv_csr {
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unsigned long sstatus;
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unsigned long sie;
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unsigned long stvec;
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unsigned long sscratch;
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unsigned long sepc;
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unsigned long scause;
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unsigned long stval;
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unsigned long sip;
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unsigned long satp;
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unsigned long scounteren;
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};
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/* TIMER registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
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struct kvm_riscv_timer {
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__u64 frequency;
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__u64 time;
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__u64 compare;
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__u64 state;
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};
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/* Possible states for kvm_riscv_timer */
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#define KVM_RISCV_TIMER_STATE_OFF 0
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#define KVM_RISCV_TIMER_STATE_ON 1
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#define KVM_REG_SIZE(id) \
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(1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
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/* If you need to interpret the index values, here is the key: */
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#define KVM_REG_RISCV_TYPE_MASK 0x00000000FF000000
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#define KVM_REG_RISCV_TYPE_SHIFT 24
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/* Config registers are mapped as type 1 */
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#define KVM_REG_RISCV_CONFIG (0x01 << KVM_REG_RISCV_TYPE_SHIFT)
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#define KVM_REG_RISCV_CONFIG_REG(name) \
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(offsetof(struct kvm_riscv_config, name) / sizeof(unsigned long))
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/* Core registers are mapped as type 2 */
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#define KVM_REG_RISCV_CORE (0x02 << KVM_REG_RISCV_TYPE_SHIFT)
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#define KVM_REG_RISCV_CORE_REG(name) \
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(offsetof(struct kvm_riscv_core, name) / sizeof(unsigned long))
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/* Control and status registers are mapped as type 3 */
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#define KVM_REG_RISCV_CSR (0x03 << KVM_REG_RISCV_TYPE_SHIFT)
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#define KVM_REG_RISCV_CSR_REG(name) \
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(offsetof(struct kvm_riscv_csr, name) / sizeof(unsigned long))
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/* Timer registers are mapped as type 4 */
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#define KVM_REG_RISCV_TIMER (0x04 << KVM_REG_RISCV_TYPE_SHIFT)
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#define KVM_REG_RISCV_TIMER_REG(name) \
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(offsetof(struct kvm_riscv_timer, name) / sizeof(__u64))
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/* F extension registers are mapped as type 5 */
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#define KVM_REG_RISCV_FP_F (0x05 << KVM_REG_RISCV_TYPE_SHIFT)
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#define KVM_REG_RISCV_FP_F_REG(name) \
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(offsetof(struct __riscv_f_ext_state, name) / sizeof(__u32))
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/* D extension registers are mapped as type 6 */
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#define KVM_REG_RISCV_FP_D (0x06 << KVM_REG_RISCV_TYPE_SHIFT)
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#define KVM_REG_RISCV_FP_D_REG(name) \
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(offsetof(struct __riscv_d_ext_state, name) / sizeof(__u64))
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#endif
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#endif /* __LINUX_KVM_RISCV_H */
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