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		97ba42230b
		
	
	
	
	
		
			
			Microchip PolarFire SoC integrates a DMA engine that supports: * Independent concurrent DMA transfers using 4 DMA channels * Generation of interrupts on various conditions during execution which is actually an IP reused from the SiFive FU540 chip. This creates a model to support both polling and interrupt modes. Signed-off-by: Bin Meng <bin.meng@windriver.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-10-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
		
			
				
	
	
		
			58 lines
		
	
	
		
			1.6 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			58 lines
		
	
	
		
			1.6 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * SiFive Platform DMA emulation
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|  *
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|  * Copyright (c) 2020 Wind River Systems, Inc.
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|  *
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|  * Author:
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|  *   Bin Meng <bin.meng@windriver.com>
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|  *
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|  * This program is free software; you can redistribute it and/or
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|  * modify it under the terms of the GNU General Public License as
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|  * published by the Free Software Foundation; either version 2 or
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|  * (at your option) version 3 of the License.
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|  *
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|  * This program is distributed in the hope that it will be useful,
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|  * but WITHOUT ANY WARRANTY; without even the implied warranty of
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|  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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|  * GNU General Public License for more details.
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|  *
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|  * You should have received a copy of the GNU General Public License along
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|  * with this program; if not, see <http://www.gnu.org/licenses/>.
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|  */
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| 
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| #ifndef SIFIVE_PDMA_H
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| #define SIFIVE_PDMA_H
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| 
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| struct sifive_pdma_chan {
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|     uint32_t control;
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|     uint32_t next_config;
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|     uint64_t next_bytes;
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|     uint64_t next_dst;
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|     uint64_t next_src;
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|     uint32_t exec_config;
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|     uint64_t exec_bytes;
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|     uint64_t exec_dst;
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|     uint64_t exec_src;
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|     int state;
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| };
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| 
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| #define SIFIVE_PDMA_CHANS           4
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| #define SIFIVE_PDMA_IRQS            (SIFIVE_PDMA_CHANS * 2)
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| #define SIFIVE_PDMA_REG_SIZE        0x100000
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| #define SIFIVE_PDMA_CHAN_NO(reg)    ((reg & (SIFIVE_PDMA_REG_SIZE - 1)) >> 12)
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| 
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| typedef struct SiFivePDMAState {
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|     SysBusDevice parent;
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|     MemoryRegion iomem;
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|     qemu_irq irq[SIFIVE_PDMA_IRQS];
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| 
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|     struct sifive_pdma_chan chan[SIFIVE_PDMA_CHANS];
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| } SiFivePDMAState;
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| 
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| #define TYPE_SIFIVE_PDMA    "sifive.pdma"
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| 
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| #define SIFIVE_PDMA(obj)    \
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|     OBJECT_CHECK(SiFivePDMAState, (obj), TYPE_SIFIVE_PDMA)
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| 
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| #endif /* SIFIVE_PDMA_H */
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