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5aec3247c1
The sifive_u machine already marks its ROM readonly however it has the wrong base address for its mask ROM. This patch fixes the sifive_u mask ROM base address. This commit makes all other boards consistently use mask_rom as the variable name for their ROMs. Boards that use device tree now check that that the device tree fits in the assigned ROM space using the new qemu_fdt_totalsize(void *fdt) interface, adding a bounds check and error message. This can detect truncation. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Alistair Francis <Alistair.Francis@wdc.com>
201 lines
7.7 KiB
C
201 lines
7.7 KiB
C
/*
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* QEMU RISC-V Board Compatible with SiFive Freedom E SDK
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*
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* Copyright (c) 2017 SiFive, Inc.
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*
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* Provides a board compatible with the SiFive Freedom E SDK:
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*
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* 0) UART
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* 1) CLINT (Core Level Interruptor)
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* 2) PLIC (Platform Level Interrupt Controller)
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* 3) PRCI (Power, Reset, Clock, Interrupt)
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* 4) Registers emulated as RAM: AON, GPIO, QSPI, PWM
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* 5) Flash memory emulated as RAM
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*
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* The Mask ROM reset vector jumps to the flash payload at 0x2040_0000.
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* The OTP ROM and Flash boot code will be emulated in a future version.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/error-report.h"
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#include "qapi/error.h"
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#include "hw/hw.h"
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#include "hw/boards.h"
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#include "hw/loader.h"
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#include "hw/sysbus.h"
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#include "hw/char/serial.h"
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#include "target/riscv/cpu.h"
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#include "hw/riscv/riscv_hart.h"
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#include "hw/riscv/sifive_plic.h"
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#include "hw/riscv/sifive_clint.h"
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#include "hw/riscv/sifive_prci.h"
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#include "hw/riscv/sifive_uart.h"
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#include "hw/riscv/sifive_e.h"
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#include "chardev/char.h"
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#include "sysemu/arch_init.h"
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#include "exec/address-spaces.h"
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#include "elf.h"
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static const struct MemmapEntry {
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hwaddr base;
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hwaddr size;
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} sifive_e_memmap[] = {
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[SIFIVE_E_DEBUG] = { 0x0, 0x100 },
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[SIFIVE_E_MROM] = { 0x1000, 0x2000 },
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[SIFIVE_E_OTP] = { 0x20000, 0x2000 },
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[SIFIVE_E_CLINT] = { 0x2000000, 0x10000 },
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[SIFIVE_E_PLIC] = { 0xc000000, 0x4000000 },
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[SIFIVE_E_AON] = { 0x10000000, 0x8000 },
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[SIFIVE_E_PRCI] = { 0x10008000, 0x8000 },
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[SIFIVE_E_OTP_CTRL] = { 0x10010000, 0x1000 },
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[SIFIVE_E_GPIO0] = { 0x10012000, 0x1000 },
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[SIFIVE_E_UART0] = { 0x10013000, 0x1000 },
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[SIFIVE_E_QSPI0] = { 0x10014000, 0x1000 },
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[SIFIVE_E_PWM0] = { 0x10015000, 0x1000 },
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[SIFIVE_E_UART1] = { 0x10023000, 0x1000 },
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[SIFIVE_E_QSPI1] = { 0x10024000, 0x1000 },
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[SIFIVE_E_PWM1] = { 0x10025000, 0x1000 },
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[SIFIVE_E_QSPI2] = { 0x10034000, 0x1000 },
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[SIFIVE_E_PWM2] = { 0x10035000, 0x1000 },
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[SIFIVE_E_XIP] = { 0x20000000, 0x20000000 },
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[SIFIVE_E_DTIM] = { 0x80000000, 0x4000 }
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};
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static uint64_t load_kernel(const char *kernel_filename)
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{
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uint64_t kernel_entry, kernel_high;
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if (load_elf(kernel_filename, NULL, NULL,
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&kernel_entry, NULL, &kernel_high,
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0, EM_RISCV, 1, 0) < 0) {
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error_report("qemu: could not load kernel '%s'", kernel_filename);
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exit(1);
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}
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return kernel_entry;
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}
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static void sifive_mmio_emulate(MemoryRegion *parent, const char *name,
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uintptr_t offset, uintptr_t length)
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{
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MemoryRegion *mock_mmio = g_new(MemoryRegion, 1);
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memory_region_init_ram(mock_mmio, NULL, name, length, &error_fatal);
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memory_region_add_subregion(parent, offset, mock_mmio);
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}
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static void riscv_sifive_e_init(MachineState *machine)
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{
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const struct MemmapEntry *memmap = sifive_e_memmap;
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SiFiveEState *s = g_new0(SiFiveEState, 1);
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MemoryRegion *sys_mem = get_system_memory();
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MemoryRegion *main_mem = g_new(MemoryRegion, 1);
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MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
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MemoryRegion *xip_mem = g_new(MemoryRegion, 1);
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int i;
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/* Initialize SOC */
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object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY);
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object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
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&error_abort);
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object_property_set_str(OBJECT(&s->soc), SIFIVE_E_CPU, "cpu-type",
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&error_abort);
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object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
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&error_abort);
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object_property_set_bool(OBJECT(&s->soc), true, "realized",
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&error_abort);
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/* Data Tightly Integrated Memory */
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memory_region_init_ram(main_mem, NULL, "riscv.sifive.e.ram",
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memmap[SIFIVE_E_DTIM].size, &error_fatal);
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memory_region_add_subregion(sys_mem,
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memmap[SIFIVE_E_DTIM].base, main_mem);
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/* Mask ROM */
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memory_region_init_rom(mask_rom, NULL, "riscv.sifive.e.mrom",
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memmap[SIFIVE_E_MROM].size, &error_fatal);
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memory_region_add_subregion(sys_mem,
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memmap[SIFIVE_E_MROM].base, mask_rom);
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/* MMIO */
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s->plic = sifive_plic_create(memmap[SIFIVE_E_PLIC].base,
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(char *)SIFIVE_E_PLIC_HART_CONFIG,
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SIFIVE_E_PLIC_NUM_SOURCES,
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SIFIVE_E_PLIC_NUM_PRIORITIES,
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SIFIVE_E_PLIC_PRIORITY_BASE,
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SIFIVE_E_PLIC_PENDING_BASE,
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SIFIVE_E_PLIC_ENABLE_BASE,
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SIFIVE_E_PLIC_ENABLE_STRIDE,
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SIFIVE_E_PLIC_CONTEXT_BASE,
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SIFIVE_E_PLIC_CONTEXT_STRIDE,
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memmap[SIFIVE_E_PLIC].size);
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sifive_clint_create(memmap[SIFIVE_E_CLINT].base,
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memmap[SIFIVE_E_CLINT].size, smp_cpus,
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SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
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sifive_mmio_emulate(sys_mem, "riscv.sifive.e.aon",
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memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size);
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sifive_prci_create(memmap[SIFIVE_E_PRCI].base);
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sifive_mmio_emulate(sys_mem, "riscv.sifive.e.gpio0",
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memmap[SIFIVE_E_GPIO0].base, memmap[SIFIVE_E_GPIO0].size);
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sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART0].base,
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serial_hd(0), SIFIVE_PLIC(s->plic)->irqs[SIFIVE_E_UART0_IRQ]);
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sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi0",
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memmap[SIFIVE_E_QSPI0].base, memmap[SIFIVE_E_QSPI0].size);
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sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm0",
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memmap[SIFIVE_E_PWM0].base, memmap[SIFIVE_E_PWM0].size);
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/* sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART1].base,
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serial_hd(1), SIFIVE_PLIC(s->plic)->irqs[SIFIVE_E_UART1_IRQ]); */
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sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi1",
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memmap[SIFIVE_E_QSPI1].base, memmap[SIFIVE_E_QSPI1].size);
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sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm1",
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memmap[SIFIVE_E_PWM1].base, memmap[SIFIVE_E_PWM1].size);
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sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi2",
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memmap[SIFIVE_E_QSPI2].base, memmap[SIFIVE_E_QSPI2].size);
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sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm2",
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memmap[SIFIVE_E_PWM2].base, memmap[SIFIVE_E_PWM2].size);
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/* Flash memory */
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memory_region_init_ram(xip_mem, NULL, "riscv.sifive.e.xip",
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memmap[SIFIVE_E_XIP].size, &error_fatal);
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memory_region_set_readonly(xip_mem, true);
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memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_XIP].base, xip_mem);
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/* Mask ROM reset vector */
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uint32_t reset_vec[2] = {
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0x204002b7, /* 0x1000: lui t0,0x20400 */
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0x00028067, /* 0x1004: jr t0 */
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};
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/* copy in the reset vector in little_endian byte order */
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for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
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reset_vec[i] = cpu_to_le32(reset_vec[i]);
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}
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rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
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memmap[SIFIVE_E_MROM].base, &address_space_memory);
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if (machine->kernel_filename) {
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load_kernel(machine->kernel_filename);
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}
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}
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static void riscv_sifive_e_machine_init(MachineClass *mc)
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{
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mc->desc = "RISC-V Board compatible with SiFive E SDK";
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mc->init = riscv_sifive_e_init;
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mc->max_cpus = 1;
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}
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DEFINE_MACHINE("sifive_e", riscv_sifive_e_machine_init)
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