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d15188ddcf
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: KONRAD Frederic <frederic.konrad@adacore.com> Message-Id: <20200331105048.27989-5-f4bug@amsat.org>
302 lines
10 KiB
C
302 lines
10 KiB
C
/*
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* GRLIB AHB APB PNP
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*
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* Copyright (C) 2019 AdaCore
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*
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* Developed by :
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* Frederic Konrad <frederic.konrad@adacore.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "hw/sysbus.h"
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#include "hw/misc/grlib_ahb_apb_pnp.h"
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#include "trace.h"
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#define GRLIB_PNP_VENDOR_SHIFT (24)
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#define GRLIB_PNP_VENDOR_SIZE (8)
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#define GRLIB_PNP_DEV_SHIFT (12)
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#define GRLIB_PNP_DEV_SIZE (12)
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#define GRLIB_PNP_VER_SHIFT (5)
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#define GRLIB_PNP_VER_SIZE (5)
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#define GRLIB_PNP_IRQ_SHIFT (0)
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#define GRLIB_PNP_IRQ_SIZE (5)
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#define GRLIB_PNP_ADDR_SHIFT (20)
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#define GRLIB_PNP_ADDR_SIZE (12)
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#define GRLIB_PNP_MASK_SHIFT (4)
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#define GRLIB_PNP_MASK_SIZE (12)
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#define GRLIB_AHB_DEV_ADDR_SHIFT (20)
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#define GRLIB_AHB_DEV_ADDR_SIZE (12)
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#define GRLIB_AHB_ENTRY_SIZE (0x20)
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#define GRLIB_AHB_MAX_DEV (64)
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#define GRLIB_AHB_SLAVE_OFFSET (0x800)
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#define GRLIB_APB_DEV_ADDR_SHIFT (8)
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#define GRLIB_APB_DEV_ADDR_SIZE (12)
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#define GRLIB_APB_ENTRY_SIZE (0x08)
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#define GRLIB_APB_MAX_DEV (512)
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#define GRLIB_PNP_MAX_REGS (0x1000)
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typedef struct AHBPnp {
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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uint32_t regs[GRLIB_PNP_MAX_REGS >> 2];
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uint8_t master_count;
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uint8_t slave_count;
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} AHBPnp;
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void grlib_ahb_pnp_add_entry(AHBPnp *dev, uint32_t address, uint32_t mask,
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uint8_t vendor, uint16_t device, int slave,
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int type)
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{
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unsigned int reg_start;
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/*
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* AHB entries look like this:
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*
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* 31 -------- 23 -------- 11 ----- 9 -------- 4 --- 0
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* | VENDOR ID | DEVICE ID | IRQ ? | VERSION | IRQ |
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* --------------------------------------------------
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* | USER |
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* --------------------------------------------------
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* | USER |
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* --------------------------------------------------
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* | USER |
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* --------------------------------------------------
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* | USER |
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* --------------------------------------------------
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* 31 ----------- 20 --- 15 ----------------- 3 ---- 0
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* | ADDR[31..12] | 00PC | MASK | TYPE |
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* --------------------------------------------------
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* 31 ----------- 20 --- 15 ----------------- 3 ---- 0
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* | ADDR[31..12] | 00PC | MASK | TYPE |
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* --------------------------------------------------
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* 31 ----------- 20 --- 15 ----------------- 3 ---- 0
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* | ADDR[31..12] | 00PC | MASK | TYPE |
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* --------------------------------------------------
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* 31 ----------- 20 --- 15 ----------------- 3 ---- 0
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* | ADDR[31..12] | 00PC | MASK | TYPE |
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* --------------------------------------------------
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*/
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if (slave) {
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assert(dev->slave_count < GRLIB_AHB_MAX_DEV);
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reg_start = (GRLIB_AHB_SLAVE_OFFSET
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+ (dev->slave_count * GRLIB_AHB_ENTRY_SIZE)) >> 2;
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dev->slave_count++;
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} else {
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assert(dev->master_count < GRLIB_AHB_MAX_DEV);
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reg_start = (dev->master_count * GRLIB_AHB_ENTRY_SIZE) >> 2;
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dev->master_count++;
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}
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dev->regs[reg_start] = deposit32(dev->regs[reg_start],
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GRLIB_PNP_VENDOR_SHIFT,
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GRLIB_PNP_VENDOR_SIZE,
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vendor);
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dev->regs[reg_start] = deposit32(dev->regs[reg_start],
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GRLIB_PNP_DEV_SHIFT,
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GRLIB_PNP_DEV_SIZE,
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device);
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reg_start += 4;
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/* AHB Memory Space */
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dev->regs[reg_start] = type;
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dev->regs[reg_start] = deposit32(dev->regs[reg_start],
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GRLIB_PNP_ADDR_SHIFT,
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GRLIB_PNP_ADDR_SIZE,
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extract32(address,
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GRLIB_AHB_DEV_ADDR_SHIFT,
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GRLIB_AHB_DEV_ADDR_SIZE));
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dev->regs[reg_start] = deposit32(dev->regs[reg_start],
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GRLIB_PNP_MASK_SHIFT,
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GRLIB_PNP_MASK_SIZE,
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mask);
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}
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static uint64_t grlib_ahb_pnp_read(void *opaque, hwaddr offset, unsigned size)
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{
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AHBPnp *ahb_pnp = GRLIB_AHB_PNP(opaque);
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uint32_t val;
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val = ahb_pnp->regs[offset >> 2];
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trace_grlib_ahb_pnp_read(offset, val);
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return val;
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}
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static void grlib_ahb_pnp_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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qemu_log_mask(LOG_UNIMP, "%s not implemented\n", __func__);
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}
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static const MemoryRegionOps grlib_ahb_pnp_ops = {
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.read = grlib_ahb_pnp_read,
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.write = grlib_ahb_pnp_write,
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.endianness = DEVICE_BIG_ENDIAN,
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static void grlib_ahb_pnp_realize(DeviceState *dev, Error **errp)
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{
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AHBPnp *ahb_pnp = GRLIB_AHB_PNP(dev);
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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memory_region_init_io(&ahb_pnp->iomem, OBJECT(dev), &grlib_ahb_pnp_ops,
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ahb_pnp, TYPE_GRLIB_AHB_PNP, GRLIB_PNP_MAX_REGS);
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sysbus_init_mmio(sbd, &ahb_pnp->iomem);
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}
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static void grlib_ahb_pnp_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = grlib_ahb_pnp_realize;
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}
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static const TypeInfo grlib_ahb_pnp_info = {
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.name = TYPE_GRLIB_AHB_PNP,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(AHBPnp),
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.class_init = grlib_ahb_pnp_class_init,
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};
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/* APBPnp */
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typedef struct APBPnp {
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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uint32_t regs[GRLIB_PNP_MAX_REGS >> 2];
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uint32_t entry_count;
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} APBPnp;
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void grlib_apb_pnp_add_entry(APBPnp *dev, uint32_t address, uint32_t mask,
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uint8_t vendor, uint16_t device, uint8_t version,
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uint8_t irq, int type)
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{
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unsigned int reg_start;
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/*
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* APB entries look like this:
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*
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* 31 -------- 23 -------- 11 ----- 9 ------- 4 --- 0
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* | VENDOR ID | DEVICE ID | IRQ ? | VERSION | IRQ |
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*
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* 31 ---------- 20 --- 15 ----------------- 3 ---- 0
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* | ADDR[20..8] | 0000 | MASK | TYPE |
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*/
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assert(dev->entry_count < GRLIB_APB_MAX_DEV);
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reg_start = (dev->entry_count * GRLIB_APB_ENTRY_SIZE) >> 2;
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dev->entry_count++;
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dev->regs[reg_start] = deposit32(dev->regs[reg_start],
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GRLIB_PNP_VENDOR_SHIFT,
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GRLIB_PNP_VENDOR_SIZE,
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vendor);
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dev->regs[reg_start] = deposit32(dev->regs[reg_start],
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GRLIB_PNP_DEV_SHIFT,
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GRLIB_PNP_DEV_SIZE,
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device);
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dev->regs[reg_start] = deposit32(dev->regs[reg_start],
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GRLIB_PNP_VER_SHIFT,
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GRLIB_PNP_VER_SIZE,
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version);
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dev->regs[reg_start] = deposit32(dev->regs[reg_start],
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GRLIB_PNP_IRQ_SHIFT,
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GRLIB_PNP_IRQ_SIZE,
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irq);
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reg_start += 1;
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dev->regs[reg_start] = type;
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dev->regs[reg_start] = deposit32(dev->regs[reg_start],
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GRLIB_PNP_ADDR_SHIFT,
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GRLIB_PNP_ADDR_SIZE,
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extract32(address,
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GRLIB_APB_DEV_ADDR_SHIFT,
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GRLIB_APB_DEV_ADDR_SIZE));
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dev->regs[reg_start] = deposit32(dev->regs[reg_start],
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GRLIB_PNP_MASK_SHIFT,
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GRLIB_PNP_MASK_SIZE,
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mask);
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}
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static uint64_t grlib_apb_pnp_read(void *opaque, hwaddr offset, unsigned size)
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{
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APBPnp *apb_pnp = GRLIB_APB_PNP(opaque);
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uint32_t val;
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val = apb_pnp->regs[offset >> 2];
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trace_grlib_apb_pnp_read(offset, val);
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return val;
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}
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static void grlib_apb_pnp_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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qemu_log_mask(LOG_UNIMP, "%s not implemented\n", __func__);
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}
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static const MemoryRegionOps grlib_apb_pnp_ops = {
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.read = grlib_apb_pnp_read,
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.write = grlib_apb_pnp_write,
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.endianness = DEVICE_BIG_ENDIAN,
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static void grlib_apb_pnp_realize(DeviceState *dev, Error **errp)
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{
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APBPnp *apb_pnp = GRLIB_APB_PNP(dev);
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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memory_region_init_io(&apb_pnp->iomem, OBJECT(dev), &grlib_apb_pnp_ops,
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apb_pnp, TYPE_GRLIB_APB_PNP, GRLIB_PNP_MAX_REGS);
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sysbus_init_mmio(sbd, &apb_pnp->iomem);
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}
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static void grlib_apb_pnp_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = grlib_apb_pnp_realize;
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}
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static const TypeInfo grlib_apb_pnp_info = {
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.name = TYPE_GRLIB_APB_PNP,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(APBPnp),
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.class_init = grlib_apb_pnp_class_init,
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};
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static void grlib_ahb_apb_pnp_register_types(void)
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{
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type_register_static(&grlib_ahb_pnp_info);
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type_register_static(&grlib_apb_pnp_info);
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}
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type_init(grlib_ahb_apb_pnp_register_types)
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