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3b97c01e9c
Implement a virtual memory device for the TPM Physical Presence interface. The memory is located at 0xFED45000 and used by ACPI to send messages to the firmware (BIOS) and by the firmware to provide parameters for each one of the supported codes. This interface should be used by all TPM devices on x86 and can be added by calling tpm_ppi_init_io(). Note: bios_linker cannot be used to allocate the PPI memory region, since the reserved memory should stay stable across reboots, and might be needed before the ACPI tables are installed. Signed-off-by: Stefan Berger <stefanb@linux.vnet.ibm.com> Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Tested-by: Stefan Berger <stefanb@linux.ibm.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
198 lines
6.9 KiB
C
198 lines
6.9 KiB
C
/*
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* tpm.h - TPM ACPI definitions
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*
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* Copyright (C) 2014 IBM Corporation
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*
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* Authors:
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* Stefan Berger <stefanb@us.ibm.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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* Implementation of the TIS interface according to specs found at
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* http://www.trustedcomputinggroup.org
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*
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*/
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#ifndef HW_ACPI_TPM_H
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#define HW_ACPI_TPM_H
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#include "qemu/units.h"
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#include "hw/registerfields.h"
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#define TPM_TIS_ADDR_BASE 0xFED40000
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#define TPM_TIS_ADDR_SIZE 0x5000
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#define TPM_TIS_IRQ 5
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#define TPM_TIS_NUM_LOCALITIES 5 /* per spec */
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#define TPM_TIS_LOCALITY_SHIFT 12
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/* tis registers */
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#define TPM_TIS_REG_ACCESS 0x00
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#define TPM_TIS_REG_INT_ENABLE 0x08
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#define TPM_TIS_REG_INT_VECTOR 0x0c
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#define TPM_TIS_REG_INT_STATUS 0x10
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#define TPM_TIS_REG_INTF_CAPABILITY 0x14
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#define TPM_TIS_REG_STS 0x18
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#define TPM_TIS_REG_DATA_FIFO 0x24
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#define TPM_TIS_REG_INTERFACE_ID 0x30
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#define TPM_TIS_REG_DATA_XFIFO 0x80
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#define TPM_TIS_REG_DATA_XFIFO_END 0xbc
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#define TPM_TIS_REG_DID_VID 0xf00
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#define TPM_TIS_REG_RID 0xf04
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/* vendor-specific registers */
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#define TPM_TIS_REG_DEBUG 0xf90
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#define TPM_TIS_STS_TPM_FAMILY_MASK (0x3 << 26)/* TPM 2.0 */
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#define TPM_TIS_STS_TPM_FAMILY1_2 (0 << 26) /* TPM 2.0 */
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#define TPM_TIS_STS_TPM_FAMILY2_0 (1 << 26) /* TPM 2.0 */
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#define TPM_TIS_STS_RESET_ESTABLISHMENT_BIT (1 << 25) /* TPM 2.0 */
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#define TPM_TIS_STS_COMMAND_CANCEL (1 << 24) /* TPM 2.0 */
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#define TPM_TIS_STS_VALID (1 << 7)
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#define TPM_TIS_STS_COMMAND_READY (1 << 6)
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#define TPM_TIS_STS_TPM_GO (1 << 5)
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#define TPM_TIS_STS_DATA_AVAILABLE (1 << 4)
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#define TPM_TIS_STS_EXPECT (1 << 3)
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#define TPM_TIS_STS_SELFTEST_DONE (1 << 2)
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#define TPM_TIS_STS_RESPONSE_RETRY (1 << 1)
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#define TPM_TIS_BURST_COUNT_SHIFT 8
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#define TPM_TIS_BURST_COUNT(X) \
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((X) << TPM_TIS_BURST_COUNT_SHIFT)
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#define TPM_TIS_ACCESS_TPM_REG_VALID_STS (1 << 7)
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#define TPM_TIS_ACCESS_ACTIVE_LOCALITY (1 << 5)
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#define TPM_TIS_ACCESS_BEEN_SEIZED (1 << 4)
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#define TPM_TIS_ACCESS_SEIZE (1 << 3)
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#define TPM_TIS_ACCESS_PENDING_REQUEST (1 << 2)
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#define TPM_TIS_ACCESS_REQUEST_USE (1 << 1)
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#define TPM_TIS_ACCESS_TPM_ESTABLISHMENT (1 << 0)
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#define TPM_TIS_INT_ENABLED (1 << 31)
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#define TPM_TIS_INT_DATA_AVAILABLE (1 << 0)
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#define TPM_TIS_INT_STS_VALID (1 << 1)
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#define TPM_TIS_INT_LOCALITY_CHANGED (1 << 2)
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#define TPM_TIS_INT_COMMAND_READY (1 << 7)
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#define TPM_TIS_INT_POLARITY_MASK (3 << 3)
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#define TPM_TIS_INT_POLARITY_LOW_LEVEL (1 << 3)
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#define TPM_TIS_INTERRUPTS_SUPPORTED (TPM_TIS_INT_LOCALITY_CHANGED | \
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TPM_TIS_INT_DATA_AVAILABLE | \
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TPM_TIS_INT_STS_VALID | \
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TPM_TIS_INT_COMMAND_READY)
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#define TPM_TIS_CAP_INTERFACE_VERSION1_3 (2 << 28)
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#define TPM_TIS_CAP_INTERFACE_VERSION1_3_FOR_TPM2_0 (3 << 28)
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#define TPM_TIS_CAP_DATA_TRANSFER_64B (3 << 9)
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#define TPM_TIS_CAP_DATA_TRANSFER_LEGACY (0 << 9)
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#define TPM_TIS_CAP_BURST_COUNT_DYNAMIC (0 << 8)
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#define TPM_TIS_CAP_INTERRUPT_LOW_LEVEL (1 << 4) /* support is mandatory */
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#define TPM_TIS_CAPABILITIES_SUPPORTED1_3 \
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(TPM_TIS_CAP_INTERRUPT_LOW_LEVEL | \
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TPM_TIS_CAP_BURST_COUNT_DYNAMIC | \
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TPM_TIS_CAP_DATA_TRANSFER_64B | \
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TPM_TIS_CAP_INTERFACE_VERSION1_3 | \
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TPM_TIS_INTERRUPTS_SUPPORTED)
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#define TPM_TIS_CAPABILITIES_SUPPORTED2_0 \
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(TPM_TIS_CAP_INTERRUPT_LOW_LEVEL | \
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TPM_TIS_CAP_BURST_COUNT_DYNAMIC | \
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TPM_TIS_CAP_DATA_TRANSFER_64B | \
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TPM_TIS_CAP_INTERFACE_VERSION1_3_FOR_TPM2_0 | \
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TPM_TIS_INTERRUPTS_SUPPORTED)
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#define TPM_TIS_IFACE_ID_INTERFACE_TIS1_3 (0xf) /* TPM 2.0 */
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#define TPM_TIS_IFACE_ID_INTERFACE_FIFO (0x0) /* TPM 2.0 */
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#define TPM_TIS_IFACE_ID_INTERFACE_VER_FIFO (0 << 4) /* TPM 2.0 */
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#define TPM_TIS_IFACE_ID_CAP_5_LOCALITIES (1 << 8) /* TPM 2.0 */
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#define TPM_TIS_IFACE_ID_CAP_TIS_SUPPORTED (1 << 13) /* TPM 2.0 */
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#define TPM_TIS_IFACE_ID_INT_SEL_LOCK (1 << 19) /* TPM 2.0 */
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#define TPM_TIS_IFACE_ID_SUPPORTED_FLAGS1_3 \
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(TPM_TIS_IFACE_ID_INTERFACE_TIS1_3 | \
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(~0u << 4)/* all of it is don't care */)
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/* if backend was a TPM 2.0: */
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#define TPM_TIS_IFACE_ID_SUPPORTED_FLAGS2_0 \
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(TPM_TIS_IFACE_ID_INTERFACE_FIFO | \
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TPM_TIS_IFACE_ID_INTERFACE_VER_FIFO | \
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TPM_TIS_IFACE_ID_CAP_5_LOCALITIES | \
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TPM_TIS_IFACE_ID_CAP_TIS_SUPPORTED)
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#define TPM_TIS_TPM_DID 0x0001
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#define TPM_TIS_TPM_VID PCI_VENDOR_ID_IBM
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#define TPM_TIS_TPM_RID 0x0001
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#define TPM_TIS_NO_DATA_BYTE 0xff
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REG32(CRB_LOC_STATE, 0x00)
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FIELD(CRB_LOC_STATE, tpmEstablished, 0, 1)
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FIELD(CRB_LOC_STATE, locAssigned, 1, 1)
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FIELD(CRB_LOC_STATE, activeLocality, 2, 3)
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FIELD(CRB_LOC_STATE, reserved, 5, 2)
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FIELD(CRB_LOC_STATE, tpmRegValidSts, 7, 1)
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REG32(CRB_LOC_CTRL, 0x08)
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REG32(CRB_LOC_STS, 0x0C)
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FIELD(CRB_LOC_STS, Granted, 0, 1)
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FIELD(CRB_LOC_STS, beenSeized, 1, 1)
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REG32(CRB_INTF_ID, 0x30)
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FIELD(CRB_INTF_ID, InterfaceType, 0, 4)
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FIELD(CRB_INTF_ID, InterfaceVersion, 4, 4)
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FIELD(CRB_INTF_ID, CapLocality, 8, 1)
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FIELD(CRB_INTF_ID, CapCRBIdleBypass, 9, 1)
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FIELD(CRB_INTF_ID, Reserved1, 10, 1)
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FIELD(CRB_INTF_ID, CapDataXferSizeSupport, 11, 2)
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FIELD(CRB_INTF_ID, CapFIFO, 13, 1)
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FIELD(CRB_INTF_ID, CapCRB, 14, 1)
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FIELD(CRB_INTF_ID, CapIFRes, 15, 2)
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FIELD(CRB_INTF_ID, InterfaceSelector, 17, 2)
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FIELD(CRB_INTF_ID, IntfSelLock, 19, 1)
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FIELD(CRB_INTF_ID, Reserved2, 20, 4)
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FIELD(CRB_INTF_ID, RID, 24, 8)
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REG32(CRB_INTF_ID2, 0x34)
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FIELD(CRB_INTF_ID2, VID, 0, 16)
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FIELD(CRB_INTF_ID2, DID, 16, 16)
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REG32(CRB_CTRL_EXT, 0x38)
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REG32(CRB_CTRL_REQ, 0x40)
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REG32(CRB_CTRL_STS, 0x44)
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FIELD(CRB_CTRL_STS, tpmSts, 0, 1)
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FIELD(CRB_CTRL_STS, tpmIdle, 1, 1)
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REG32(CRB_CTRL_CANCEL, 0x48)
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REG32(CRB_CTRL_START, 0x4C)
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REG32(CRB_INT_ENABLED, 0x50)
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REG32(CRB_INT_STS, 0x54)
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REG32(CRB_CTRL_CMD_SIZE, 0x58)
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REG32(CRB_CTRL_CMD_LADDR, 0x5C)
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REG32(CRB_CTRL_CMD_HADDR, 0x60)
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REG32(CRB_CTRL_RSP_SIZE, 0x64)
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REG32(CRB_CTRL_RSP_ADDR, 0x68)
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REG32(CRB_DATA_BUFFER, 0x80)
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#define TPM_CRB_ADDR_BASE 0xFED40000
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#define TPM_CRB_ADDR_SIZE 0x1000
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#define TPM_CRB_ADDR_CTRL (TPM_CRB_ADDR_BASE + A_CRB_CTRL_REQ)
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#define TPM_CRB_R_MAX R_CRB_DATA_BUFFER
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#define TPM_LOG_AREA_MINIMUM_SIZE (64 * KiB)
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#define TPM_TCPA_ACPI_CLASS_CLIENT 0
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#define TPM_TCPA_ACPI_CLASS_SERVER 1
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#define TPM2_ACPI_CLASS_CLIENT 0
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#define TPM2_ACPI_CLASS_SERVER 1
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#define TPM2_START_METHOD_MMIO 6
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#define TPM2_START_METHOD_CRB 7
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/*
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* Physical Presence Interface
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*/
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#define TPM_PPI_ADDR_SIZE 0x400
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#define TPM_PPI_ADDR_BASE 0xFED45000
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#endif /* HW_ACPI_TPM_H */
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