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a8d2532645
No header includes qemu-common.h after this commit, as prescribed by qemu-common.h's file comment. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190523143508.25387-5-armbru@redhat.com> [Rebased with conflicts resolved automatically, except for include/hw/arm/xlnx-zynqmp.h hw/arm/nrf51_soc.c hw/arm/msf2-soc.c block/qcow2-refcount.c block/qcow2-cluster.c block/qcow2-cache.c target/arm/cpu.h target/lm32/cpu.h target/m68k/cpu.h target/mips/cpu.h target/moxie/cpu.h target/nios2/cpu.h target/openrisc/cpu.h target/riscv/cpu.h target/tilegx/cpu.h target/tricore/cpu.h target/unicore32/cpu.h target/xtensa/cpu.h; bsd-user/main.c and net/tap-bsd.c fixed up]
275 lines
8.4 KiB
C
275 lines
8.4 KiB
C
/*
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* QEMU model of the Xilinx ZynqMP Real Time Clock (RTC).
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*
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* Copyright (c) 2017 Xilinx Inc.
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*
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* Written-by: Alistair Francis <alistair.francis@xilinx.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "qemu-common.h"
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#include "hw/sysbus.h"
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#include "hw/register.h"
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#include "qemu/bitops.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "hw/ptimer.h"
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#include "qemu/cutils.h"
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#include "sysemu/sysemu.h"
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#include "trace.h"
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#include "hw/timer/xlnx-zynqmp-rtc.h"
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#ifndef XLNX_ZYNQMP_RTC_ERR_DEBUG
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#define XLNX_ZYNQMP_RTC_ERR_DEBUG 0
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#endif
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static void rtc_int_update_irq(XlnxZynqMPRTC *s)
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{
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bool pending = s->regs[R_RTC_INT_STATUS] & ~s->regs[R_RTC_INT_MASK];
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qemu_set_irq(s->irq_rtc_int, pending);
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}
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static void addr_error_int_update_irq(XlnxZynqMPRTC *s)
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{
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bool pending = s->regs[R_ADDR_ERROR] & ~s->regs[R_ADDR_ERROR_INT_MASK];
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qemu_set_irq(s->irq_addr_error_int, pending);
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}
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static uint32_t rtc_get_count(XlnxZynqMPRTC *s)
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{
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int64_t now = qemu_clock_get_ns(rtc_clock);
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return s->tick_offset + now / NANOSECONDS_PER_SECOND;
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}
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static uint64_t current_time_postr(RegisterInfo *reg, uint64_t val64)
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{
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XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
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return rtc_get_count(s);
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}
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static void rtc_int_status_postw(RegisterInfo *reg, uint64_t val64)
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{
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XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
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rtc_int_update_irq(s);
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}
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static uint64_t rtc_int_en_prew(RegisterInfo *reg, uint64_t val64)
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{
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XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
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s->regs[R_RTC_INT_MASK] &= (uint32_t) ~val64;
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rtc_int_update_irq(s);
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return 0;
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}
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static uint64_t rtc_int_dis_prew(RegisterInfo *reg, uint64_t val64)
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{
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XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
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s->regs[R_RTC_INT_MASK] |= (uint32_t) val64;
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rtc_int_update_irq(s);
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return 0;
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}
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static void addr_error_postw(RegisterInfo *reg, uint64_t val64)
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{
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XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
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addr_error_int_update_irq(s);
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}
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static uint64_t addr_error_int_en_prew(RegisterInfo *reg, uint64_t val64)
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{
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XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
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s->regs[R_ADDR_ERROR_INT_MASK] &= (uint32_t) ~val64;
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addr_error_int_update_irq(s);
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return 0;
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}
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static uint64_t addr_error_int_dis_prew(RegisterInfo *reg, uint64_t val64)
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{
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XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
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s->regs[R_ADDR_ERROR_INT_MASK] |= (uint32_t) val64;
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addr_error_int_update_irq(s);
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return 0;
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}
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static const RegisterAccessInfo rtc_regs_info[] = {
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{ .name = "SET_TIME_WRITE", .addr = A_SET_TIME_WRITE,
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.unimp = MAKE_64BIT_MASK(0, 32),
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},{ .name = "SET_TIME_READ", .addr = A_SET_TIME_READ,
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.ro = 0xffffffff,
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.post_read = current_time_postr,
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},{ .name = "CALIB_WRITE", .addr = A_CALIB_WRITE,
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.unimp = MAKE_64BIT_MASK(0, 32),
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},{ .name = "CALIB_READ", .addr = A_CALIB_READ,
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.ro = 0x1fffff,
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},{ .name = "CURRENT_TIME", .addr = A_CURRENT_TIME,
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.ro = 0xffffffff,
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.post_read = current_time_postr,
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},{ .name = "CURRENT_TICK", .addr = A_CURRENT_TICK,
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.ro = 0xffff,
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},{ .name = "ALARM", .addr = A_ALARM,
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},{ .name = "RTC_INT_STATUS", .addr = A_RTC_INT_STATUS,
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.w1c = 0x3,
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.post_write = rtc_int_status_postw,
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},{ .name = "RTC_INT_MASK", .addr = A_RTC_INT_MASK,
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.reset = 0x3,
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.ro = 0x3,
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},{ .name = "RTC_INT_EN", .addr = A_RTC_INT_EN,
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.pre_write = rtc_int_en_prew,
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},{ .name = "RTC_INT_DIS", .addr = A_RTC_INT_DIS,
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.pre_write = rtc_int_dis_prew,
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},{ .name = "ADDR_ERROR", .addr = A_ADDR_ERROR,
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.w1c = 0x1,
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.post_write = addr_error_postw,
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},{ .name = "ADDR_ERROR_INT_MASK", .addr = A_ADDR_ERROR_INT_MASK,
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.reset = 0x1,
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.ro = 0x1,
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},{ .name = "ADDR_ERROR_INT_EN", .addr = A_ADDR_ERROR_INT_EN,
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.pre_write = addr_error_int_en_prew,
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},{ .name = "ADDR_ERROR_INT_DIS", .addr = A_ADDR_ERROR_INT_DIS,
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.pre_write = addr_error_int_dis_prew,
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},{ .name = "CONTROL", .addr = A_CONTROL,
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.reset = 0x1000000,
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.rsvd = 0x70fffffe,
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},{ .name = "SAFETY_CHK", .addr = A_SAFETY_CHK,
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}
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};
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static void rtc_reset(DeviceState *dev)
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{
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XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(dev);
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
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register_reset(&s->regs_info[i]);
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}
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rtc_int_update_irq(s);
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addr_error_int_update_irq(s);
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}
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static const MemoryRegionOps rtc_ops = {
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.read = register_read_memory,
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.write = register_write_memory,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static void rtc_init(Object *obj)
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{
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XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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RegisterInfoArray *reg_array;
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struct tm current_tm;
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memory_region_init(&s->iomem, obj, TYPE_XLNX_ZYNQMP_RTC,
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XLNX_ZYNQMP_RTC_R_MAX * 4);
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reg_array =
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register_init_block32(DEVICE(obj), rtc_regs_info,
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ARRAY_SIZE(rtc_regs_info),
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s->regs_info, s->regs,
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&rtc_ops,
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XLNX_ZYNQMP_RTC_ERR_DEBUG,
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XLNX_ZYNQMP_RTC_R_MAX * 4);
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memory_region_add_subregion(&s->iomem,
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0x0,
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®_array->mem);
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sysbus_init_mmio(sbd, &s->iomem);
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sysbus_init_irq(sbd, &s->irq_rtc_int);
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sysbus_init_irq(sbd, &s->irq_addr_error_int);
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qemu_get_timedate(¤t_tm, 0);
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s->tick_offset = mktimegm(¤t_tm) -
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qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND;
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trace_xlnx_zynqmp_rtc_gettime(current_tm.tm_year, current_tm.tm_mon,
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current_tm.tm_mday, current_tm.tm_hour,
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current_tm.tm_min, current_tm.tm_sec);
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}
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static int rtc_pre_save(void *opaque)
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{
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XlnxZynqMPRTC *s = opaque;
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int64_t now = qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND;
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/* Add the time at migration */
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s->tick_offset = s->tick_offset + now;
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return 0;
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}
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static int rtc_post_load(void *opaque, int version_id)
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{
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XlnxZynqMPRTC *s = opaque;
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int64_t now = qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND;
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/* Subtract the time after migration. This combined with the pre_save
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* action results in us having subtracted the time that the guest was
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* stopped to the offset.
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*/
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s->tick_offset = s->tick_offset - now;
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return 0;
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}
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static const VMStateDescription vmstate_rtc = {
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.name = TYPE_XLNX_ZYNQMP_RTC,
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.version_id = 1,
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.minimum_version_id = 1,
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.pre_save = rtc_pre_save,
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.post_load = rtc_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPRTC, XLNX_ZYNQMP_RTC_R_MAX),
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VMSTATE_UINT32(tick_offset, XlnxZynqMPRTC),
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VMSTATE_END_OF_LIST(),
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}
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};
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static void rtc_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->reset = rtc_reset;
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dc->vmsd = &vmstate_rtc;
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}
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static const TypeInfo rtc_info = {
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.name = TYPE_XLNX_ZYNQMP_RTC,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(XlnxZynqMPRTC),
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.class_init = rtc_class_init,
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.instance_init = rtc_init,
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};
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static void rtc_register_types(void)
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{
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type_register_static(&rtc_info);
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}
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type_init(rtc_register_types)
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