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Create Cluster Power Controller and add a link to the CPC MemoryRegion in GCR. Guest can enable / map CPC to any physical address by writing to the memory-mapped GCR_CPC_BASE register. Set vp-start-reset property to 1 to allow only first VP to run from reset. Others are brought up by the guest via CPC memory-mapped registers. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
45 lines
1.2 KiB
C
45 lines
1.2 KiB
C
/*
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* Coherent Processing System emulation.
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*
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* Copyright (c) 2016 Imagination Technologies
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef MIPS_CPS_H
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#define MIPS_CPS_H
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#include "hw/sysbus.h"
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#include "hw/misc/mips_cmgcr.h"
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#include "hw/misc/mips_cpc.h"
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#define TYPE_MIPS_CPS "mips-cps"
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#define MIPS_CPS(obj) OBJECT_CHECK(MIPSCPSState, (obj), TYPE_MIPS_CPS)
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typedef struct MIPSCPSState {
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SysBusDevice parent_obj;
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uint32_t num_vp;
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uint32_t num_irq;
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char *cpu_model;
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MemoryRegion container;
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MIPSGCRState gcr;
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MIPSCPCState cpc;
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} MIPSCPSState;
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qemu_irq get_cps_irq(MIPSCPSState *cps, int pin_number);
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#endif
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