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5b64db9754
This is used in OpenBIOS to define the memory layout of the NVRAM device. Whilst currently left at its default value, add the missing definition to ensure it is reserved. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
110 lines
4.2 KiB
C
110 lines
4.2 KiB
C
#ifndef HW_PPC_H
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#define HW_PPC_H
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#include "target/ppc/cpu-qom.h"
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void ppc_set_irq(PowerPCCPU *cpu, int n_IRQ, int level);
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/* PowerPC hardware exceptions management helpers */
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typedef void (*clk_setup_cb)(void *opaque, uint32_t freq);
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typedef struct clk_setup_t clk_setup_t;
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struct clk_setup_t {
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clk_setup_cb cb;
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void *opaque;
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};
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static inline void clk_setup (clk_setup_t *clk, uint32_t freq)
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{
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if (clk->cb != NULL)
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(*clk->cb)(clk->opaque, freq);
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}
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struct ppc_tb_t {
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/* Time base management */
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int64_t tb_offset; /* Compensation */
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int64_t atb_offset; /* Compensation */
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uint32_t tb_freq; /* TB frequency */
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/* Decrementer management */
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uint64_t decr_next; /* Tick for next decr interrupt */
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uint32_t decr_freq; /* decrementer frequency */
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QEMUTimer *decr_timer;
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/* Hypervisor decrementer management */
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uint64_t hdecr_next; /* Tick for next hdecr interrupt */
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QEMUTimer *hdecr_timer;
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uint64_t purr_load;
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uint64_t purr_start;
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void *opaque;
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uint32_t flags;
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};
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/* PPC Timers flags */
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#define PPC_TIMER_BOOKE (1 << 0) /* Enable Booke support */
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#define PPC_TIMER_E500 (1 << 1) /* Enable e500 support */
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#define PPC_DECR_UNDERFLOW_TRIGGERED (1 << 2) /* Decr interrupt triggered when
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* the most significant bit
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* changes from 0 to 1.
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*/
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#define PPC_DECR_ZERO_TRIGGERED (1 << 3) /* Decr interrupt triggered when
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* the decrementer reaches zero.
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*/
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#define PPC_DECR_UNDERFLOW_LEVEL (1 << 4) /* Decr interrupt active when
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* the most significant bit is 1.
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*/
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uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset);
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clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq);
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/* Embedded PowerPC DCR management */
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typedef uint32_t (*dcr_read_cb)(void *opaque, int dcrn);
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typedef void (*dcr_write_cb)(void *opaque, int dcrn, uint32_t val);
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int ppc_dcr_init (CPUPPCState *env, int (*dcr_read_error)(int dcrn),
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int (*dcr_write_error)(int dcrn));
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int ppc_dcr_register (CPUPPCState *env, int dcrn, void *opaque,
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dcr_read_cb drc_read, dcr_write_cb dcr_write);
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clk_setup_cb ppc_40x_timers_init (CPUPPCState *env, uint32_t freq,
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unsigned int decr_excp);
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/* Embedded PowerPC reset */
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void ppc40x_core_reset(PowerPCCPU *cpu);
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void ppc40x_chip_reset(PowerPCCPU *cpu);
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void ppc40x_system_reset(PowerPCCPU *cpu);
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void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
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#if defined(CONFIG_USER_ONLY)
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static inline void ppc40x_irq_init(PowerPCCPU *cpu) {}
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static inline void ppc6xx_irq_init(PowerPCCPU *cpu) {}
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static inline void ppc970_irq_init(PowerPCCPU *cpu) {}
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static inline void ppcPOWER7_irq_init(PowerPCCPU *cpu) {}
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static inline void ppce500_irq_init(PowerPCCPU *cpu) {}
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#else
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void ppc40x_irq_init(PowerPCCPU *cpu);
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void ppce500_irq_init(PowerPCCPU *cpu);
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void ppc6xx_irq_init(PowerPCCPU *cpu);
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void ppc970_irq_init(PowerPCCPU *cpu);
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void ppcPOWER7_irq_init(PowerPCCPU *cpu);
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#endif
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/* PPC machines for OpenBIOS */
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enum {
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ARCH_PREP = 0,
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ARCH_MAC99,
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ARCH_HEATHROW,
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ARCH_MAC99_U3,
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};
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#define FW_CFG_PPC_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
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#define FW_CFG_PPC_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
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#define FW_CFG_PPC_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
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#define FW_CFG_PPC_TBFREQ (FW_CFG_ARCH_LOCAL + 0x03)
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#define FW_CFG_PPC_CLOCKFREQ (FW_CFG_ARCH_LOCAL + 0x04)
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#define FW_CFG_PPC_IS_KVM (FW_CFG_ARCH_LOCAL + 0x05)
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#define FW_CFG_PPC_KVM_HC (FW_CFG_ARCH_LOCAL + 0x06)
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#define FW_CFG_PPC_KVM_PID (FW_CFG_ARCH_LOCAL + 0x07)
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#define FW_CFG_PPC_NVRAM_ADDR (FW_CFG_ARCH_LOCAL + 0x08)
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#define FW_CFG_PPC_BUSFREQ (FW_CFG_ARCH_LOCAL + 0x09)
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#define FW_CFG_PPC_NVRAM_FLAT (FW_CFG_ARCH_LOCAL + 0x0a)
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#define PPC_SERIAL_MM_BAUDBASE 399193
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/* ppc_booke.c */
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void ppc_booke_timers_init(PowerPCCPU *cpu, uint32_t freq, uint32_t flags);
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#endif
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