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The watchdog is part of NPCM7XX's timer module. Its behavior is controlled by the WTCR register in the timer. When enabled, the watchdog issues an interrupt signal after a pre-set amount of cycles, and issues a reset signal shortly after that. Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Signed-off-by: Hao Wu <wuhaotsh@google.com> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: deleted blank line at end of npcm_watchdog_timer-test.c] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
51 lines
1.5 KiB
C
51 lines
1.5 KiB
C
/*
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* Nuvoton NPCM7xx Clock Control Registers.
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*
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* Copyright 2020 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#ifndef NPCM7XX_CLK_H
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#define NPCM7XX_CLK_H
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#include "exec/memory.h"
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#include "hw/sysbus.h"
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/*
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* The reference clock frequency for the timer modules, and the SECCNT and
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* CNTR25M registers in this module, is always 25 MHz.
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*/
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#define NPCM7XX_TIMER_REF_HZ (25000000)
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/*
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* Number of registers in our device state structure. Don't change this without
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* incrementing the version_id in the vmstate.
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*/
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#define NPCM7XX_CLK_NR_REGS (0x70 / sizeof(uint32_t))
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#define NPCM7XX_WATCHDOG_RESET_GPIO_IN "npcm7xx-clk-watchdog-reset-gpio-in"
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typedef struct NPCM7xxCLKState {
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SysBusDevice parent;
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MemoryRegion iomem;
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uint32_t regs[NPCM7XX_CLK_NR_REGS];
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/* Time reference for SECCNT and CNTR25M, initialized by power on reset */
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int64_t ref_ns;
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} NPCM7xxCLKState;
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#define TYPE_NPCM7XX_CLK "npcm7xx-clk"
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#define NPCM7XX_CLK(obj) OBJECT_CHECK(NPCM7xxCLKState, (obj), TYPE_NPCM7XX_CLK)
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#endif /* NPCM7XX_CLK_H */
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