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d86d30192b
This adds just enough of a root port implementation to be able to enumerate root ports (creating the required DVSEC entries). What's not here yet is the MMIO nor the ability to write some of the DVSEC entries. This can be added with the qemu commandline by adding a rootport to a specific CXL host bridge. For example: -device cxl-rp,id=rp0,bus="cxl.0",addr=0.0,chassis=4 Like the host bridge patch, the ACPI tables aren't generated at this point and so system software cannot use it. Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20220429144110.25167-17-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
16 lines
754 B
Meson
16 lines
754 B
Meson
pci_ss = ss.source_set()
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pci_ss.add(files('pci_bridge_dev.c'))
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pci_ss.add(when: 'CONFIG_I82801B11', if_true: files('i82801b11.c'))
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pci_ss.add(when: 'CONFIG_IOH3420', if_true: files('ioh3420.c'))
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pci_ss.add(when: 'CONFIG_PCIE_PORT', if_true: files('pcie_root_port.c', 'gen_pcie_root_port.c', 'pcie_pci_bridge.c'))
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pci_ss.add(when: 'CONFIG_PXB', if_true: files('pci_expander_bridge.c'))
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pci_ss.add(when: 'CONFIG_XIO3130', if_true: files('xio3130_upstream.c', 'xio3130_downstream.c'))
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pci_ss.add(when: 'CONFIG_CXL', if_true: files('cxl_root_port.c'))
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# NewWorld PowerMac
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pci_ss.add(when: 'CONFIG_DEC_PCI', if_true: files('dec.c'))
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# Sun4u
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pci_ss.add(when: 'CONFIG_SIMBA', if_true: files('simba.c'))
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softmmu_ss.add_all(when: 'CONFIG_PCI', if_true: pci_ss)
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