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7f4faa2185
DFPU sets Invalid flag in FSR when at least one argument of FP comparison opcodes is NaN, SNaN for most opcodes, any NaN for olt/ole. Add checks for FSR and expected FSR values. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
148 lines
4.2 KiB
ArmAsm
148 lines
4.2 KiB
ArmAsm
#include "macros.inc"
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#include "fpu.h"
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test_suite fp1
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#if XCHAL_HAVE_FP
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.macro movfp fr, v
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movi a2, \v
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wfr \fr, a2
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.endm
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.macro test_ord_ex op, br, fr0, fr1, v0, v1, r, sr
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movi a2, 0
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wur a2, fsr
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movfp \fr0, \v0
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movfp \fr1, \v1
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\op \br, \fr0, \fr1
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movi a2, 0
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movi a3, 1
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movt a2, a3, \br
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assert eqi, a2, \r
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rur a2, fsr
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#if DFPU
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movi a3, \sr
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assert eq, a2, a3
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#else
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assert eqi, a2, 0
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#endif
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.endm
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.macro test_ord op, br, fr0, fr1, v0, v1, r, sr
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movi a2, 0
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wur a2, fcr
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test_ord_ex \op, \br, \fr0, \fr1, \v0, \v1, \r, \sr
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movi a2, 0x7c
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wur a2, fcr
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test_ord_ex \op, \br, \fr0, \fr1, \v0, \v1, \r, \sr
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.endm
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.macro test_ord_all op, aa, ab, ba, aPI, PIa, aN, Na, II, IN, NI, qnan_sr
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test_ord \op b0, f0, f1, 0x3f800000, 0x3f800000, \aa, FSR__ /* ord == ord */
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test_ord \op b1, f2, f3, 0x3f800000, 0x3fc00000, \ab, FSR__ /* ord < ord */
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test_ord \op b2, f4, f5, 0x3fc00000, 0x3f800000, \ba, FSR__ /* ord > ord */
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test_ord \op b3, f6, f7, 0x3f800000, 0x7f800000, \aPI, FSR__ /* ord +INF */
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test_ord \op b4, f8, f9, 0x7f800000, 0x3f800000, \PIa, FSR__ /* +INF ord */
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test_ord \op b5, f10, f11, 0x3f800000, 0xffc00001, \aN, \qnan_sr /* ord -QNaN */
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test_ord \op b6, f12, f13, 0x3f800000, 0xff800001, \aN, FSR_V /* ord -SNaN */
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test_ord \op b7, f14, f15, 0x3f800000, 0x7f800001, \aN, FSR_V /* ord +SNaN */
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test_ord \op b8, f0, f1, 0x3f800000, 0x7fc00000, \aN, \qnan_sr /* ord +QNaN */
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test_ord \op b9, f2, f3, 0xffc00001, 0x3f800000, \Na, \qnan_sr /* -QNaN ord */
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test_ord \op b10, f4, f5, 0xff800001, 0x3f800000, \Na, FSR_V /* -SNaN ord */
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test_ord \op b11, f6, f7, 0x7f800001, 0x3f800000, \Na, FSR_V /* +SNaN ord */
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test_ord \op b12, f8, f9, 0x7fc00000, 0x3f800000, \Na, \qnan_sr /* +QNaN ord */
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test_ord \op b13, f10, f11, 0x7f800000, 0x7f800000, \II, FSR__ /* +INF +INF */
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test_ord \op b14, f12, f13, 0x7f800000, 0x7fc00000, \IN, \qnan_sr /* +INF +QNaN */
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test_ord \op b15, f14, f15, 0x7fc00000, 0x7f800000, \NI, \qnan_sr /* +QNaN +INF */
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.endm
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test un_s
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movi a2, 1
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wsr a2, cpenable
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test_ord_all un.s, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1, FSR__
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test_end
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test oeq_s
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test_ord_all oeq.s, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, FSR__
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test_end
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test ueq_s
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test_ord_all ueq.s, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, FSR__
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test_end
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test olt_s
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test_ord_all olt.s, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, FSR_V
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test_end
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test ult_s
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test_ord_all ult.s, 0, 1, 0, 1, 0, 1, 1, 0, 1, 1, FSR__
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test_end
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test ole_s
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test_ord_all ole.s, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0, FSR_V
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test_end
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test ule_s
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test_ord_all ule.s, 1, 1, 0, 1, 0, 1, 1, 1, 1, 1, FSR__
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test_end
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.macro test_cond op, fr0, fr1, cr, v0, v1, r
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movfp \fr0, \v0
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movfp \fr1, \v1
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\op \fr0, \fr1, \cr
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rfr a2, \fr0
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movi a3, \r
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assert eq, a2, a3
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.endm
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test moveqz_s
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movi a3, 0
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test_cond moveqz.s, f0, f1, a3, 0, 0x3f800000, 0x3f800000
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movi a3, 1
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test_cond moveqz.s, f0, f1, a3, 0, 0x3f800000, 0
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test_end
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test movnez_s
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movi a3, 0
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test_cond movnez.s, f0, f1, a3, 0, 0x3f800000, 0
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movi a3, 1
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test_cond movnez.s, f0, f1, a3, 0, 0x3f800000, 0x3f800000
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test_end
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test movltz_s
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movi a3, -1
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test_cond movltz.s, f0, f1, a3, 0, 0x3f800000, 0x3f800000
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movi a3, 0
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test_cond movltz.s, f0, f1, a3, 0, 0x3f800000, 0
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movi a3, 1
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test_cond movltz.s, f0, f1, a3, 0, 0x3f800000, 0
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test_end
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test movgez_s
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movi a3, -1
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test_cond movgez.s, f0, f1, a3, 0, 0x3f800000, 0
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movi a3, 0
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test_cond movgez.s, f0, f1, a3, 0, 0x3f800000, 0x3f800000
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movi a3, 1
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test_cond movgez.s, f0, f1, a3, 0, 0x3f800000, 0x3f800000
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test_end
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test movf_s
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olt.s b0, f0, f0
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test_cond movf.s, f0, f1, b0, 0, 0x3f800000, 0x3f800000
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ueq.s b0, f0, f0
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test_cond movf.s, f0, f1, b0, 0, 0x3f800000, 0
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test_end
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test movt_s
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ueq.s b0, f0, f0
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test_cond movt.s, f0, f1, b0, 0, 0x3f800000, 0x3f800000
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olt.s b0, f0, f0
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test_cond movt.s, f0, f1, b0, 0, 0x3f800000, 0
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test_end
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#endif
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test_suite_end
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