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ac81ff227d
Test that madd doesn't do rounding after multiplication. Test NaN propagation rules for FPU2000 and DFPU madd opcode. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
262 lines
11 KiB
ArmAsm
262 lines
11 KiB
ArmAsm
#include "macros.inc"
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#include "fpu.h"
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test_suite fp0_arith
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#if XCHAL_HAVE_FP
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.macro movfp fr, v
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movi a2, \v
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wfr \fr, a2
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.endm
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.macro check_res fr, r, sr
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rfr a2, \fr
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dump a2
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movi a3, \r
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assert eq, a2, a3
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rur a2, fsr
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#if DFPU
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movi a3, \sr
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assert eq, a2, a3
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#else
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assert eqi, a2, 0
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#endif
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.endm
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test add_s
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movi a2, 1
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wsr a2, cpenable
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test_op2 add.s, f0, f1, f2, 0x3fc00000, 0x34400000, \
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0x3fc00002, 0x3fc00001, 0x3fc00002, 0x3fc00001, \
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FSR_I, FSR_I, FSR_I, FSR_I
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test_op2 add.s, f3, f4, f5, 0x3fc00000, 0x34a00000, \
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0x3fc00002, 0x3fc00002, 0x3fc00003, 0x3fc00002, \
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FSR_I, FSR_I, FSR_I, FSR_I
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/* MAX_FLOAT + MAX_FLOAT = +inf/MAX_FLOAT */
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test_op2 add.s, f6, f7, f8, 0x7f7fffff, 0x7f7fffff, \
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0x7f800000, 0x7f7fffff, 0x7f800000, 0x7f7fffff, \
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FSR_OI, FSR_OI, FSR_OI, FSR_OI
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test_end
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test add_s_inf
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/* 1 + +inf = +inf */
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test_op2 add.s, f6, f7, f8, 0x3fc00000, 0x7f800000, \
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0x7f800000, 0x7f800000, 0x7f800000, 0x7f800000, \
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FSR__, FSR__, FSR__, FSR__
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/* +inf + -inf = default NaN */
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test_op2 add.s, f0, f1, f2, 0x7f800000, 0xff800000, \
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0x7fc00000, 0x7fc00000, 0x7fc00000, 0x7fc00000, \
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FSR_V, FSR_V, FSR_V, FSR_V
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test_end
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#if DFPU
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test add_s_nan_dfpu
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/* 1 + QNaN = QNaN */
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test_op2 add.s, f9, f10, f11, 0x3fc00000, 0x7fc00001, \
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0x7fc00001, 0x7fc00001, 0x7fc00001, 0x7fc00001, \
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FSR__, FSR__, FSR__, FSR__
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/* 1 + SNaN = QNaN */
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test_op2 add.s, f12, f13, f14, 0x3fc00000, 0x7f800001, \
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0x7fc00001, 0x7fc00001, 0x7fc00001, 0x7fc00001, \
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FSR_V, FSR_V, FSR_V, FSR_V
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/* SNaN1 + SNaN2 = QNaN2 */
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test_op2 add.s, f15, f0, f1, 0x7f800001, 0x7fbfffff, \
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0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff, \
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FSR_V, FSR_V, FSR_V, FSR_V
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test_op2 add.s, f2, f3, f4, 0x7fbfffff, 0x7f800001, \
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0x7fc00001, 0x7fc00001, 0x7fc00001, 0x7fc00001, \
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FSR_V, FSR_V, FSR_V, FSR_V
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/* QNaN1 + SNaN2 = QNaN2 */
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test_op2 add.s, f5, f6, f7, 0x7fc00001, 0x7fbfffff, \
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0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff, \
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FSR_V, FSR_V, FSR_V, FSR_V
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/* SNaN1 + QNaN2 = QNaN2 */
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test_op2 add.s, f8, f9, f10, 0x7fbfffff, 0x7fc00001, \
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0x7fc00001, 0x7fc00001, 0x7fc00001, 0x7fc00001, \
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FSR_V, FSR_V, FSR_V, FSR_V
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test_end
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#else
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test add_s_nan_fpu2k
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/* 1 + QNaN = QNaN */
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test_op2 add.s, f9, f10, f11, 0x3fc00000, 0x7fc00001, \
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0x7fc00001, 0x7fc00001, 0x7fc00001, 0x7fc00001, \
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FSR__, FSR__, FSR__, FSR__
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/* 1 + SNaN = SNaN */
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test_op2 add.s, f12, f13, f14, 0x3fc00000, 0x7f800001, \
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0x7f800001, 0x7f800001, 0x7f800001, 0x7f800001, \
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FSR__, FSR__, FSR__, FSR__
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/* SNaN1 + SNaN2 = SNaN1 */
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test_op2 add.s, f15, f0, f1, 0x7f800001, 0x7fbfffff, \
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0x7f800001, 0x7f800001, 0x7f800001, 0x7f800001, \
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FSR__, FSR__, FSR__, FSR__
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test_op2 add.s, f2, f3, f4, 0x7fbfffff, 0x7f800001, \
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0x7fbfffff, 0x7fbfffff, 0x7fbfffff, 0x7fbfffff, \
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FSR__, FSR__, FSR__, FSR__
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/* QNaN1 + SNaN2 = QNaN1 */
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test_op2 add.s, f5, f6, f7, 0x7fc00001, 0x7fbfffff, \
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0x7fc00001, 0x7fc00001, 0x7fc00001, 0x7fc00001, \
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FSR__, FSR__, FSR__, FSR__
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/* SNaN1 + QNaN2 = SNaN1 */
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test_op2 add.s, f8, f9, f10, 0x7fbfffff, 0x7fc00001, \
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0x7fbfffff, 0x7fbfffff, 0x7fbfffff, 0x7fbfffff, \
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FSR__, FSR__, FSR__, FSR__
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test_end
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#endif
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test sub_s
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test_op2 sub.s, f0, f1, f0, 0x3f800001, 0x33800000, \
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0x3f800000, 0x3f800000, 0x3f800001, 0x3f800000, \
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FSR_I, FSR_I, FSR_I, FSR_I
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test_op2 sub.s, f0, f1, f1, 0x3f800002, 0x33800000, \
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0x3f800002, 0x3f800001, 0x3f800002, 0x3f800001, \
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FSR_I, FSR_I, FSR_I, FSR_I
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/* norm - norm = denorm */
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test_op2 sub.s, f6, f7, f8, 0x00800001, 0x00800000, \
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0x00000001, 0x00000001, 0x00000001, 0x00000001, \
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FSR__, FSR__, FSR__, FSR__
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test_end
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test mul_s
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test_op2 mul.s, f0, f1, f2, 0x3f800001, 0x3f800001, \
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0x3f800002, 0x3f800002, 0x3f800003, 0x3f800002, \
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FSR_I, FSR_I, FSR_I, FSR_I
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/* MAX_FLOAT/2 * MAX_FLOAT/2 = +inf/MAX_FLOAT */
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test_op2 mul.s, f6, f7, f8, 0x7f000000, 0x7f000000, \
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0x7f800000, 0x7f7fffff, 0x7f800000, 0x7f7fffff, \
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FSR_OI, FSR_OI, FSR_OI, FSR_OI
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/* min norm * min norm = 0/denorm */
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test_op2 mul.s, f6, f7, f8, 0x00800001, 0x00800000, \
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0x00000000, 0x00000000, 0x00000001, 0x00000000, \
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FSR_UI, FSR_UI, FSR_UI, FSR_UI
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/* inf * 0 = default NaN */
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test_op2 mul.s, f6, f7, f8, 0x7f800000, 0x00000000, \
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0x7fc00000, 0x7fc00000, 0x7fc00000, 0x7fc00000, \
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FSR_V, FSR_V, FSR_V, FSR_V
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test_end
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test madd_s
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test_op3 madd.s, f0, f1, f2, f0, 0, 0x3f800001, 0x3f800001, \
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0x3f800002, 0x3f800002, 0x3f800003, 0x3f800002, \
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FSR_I, FSR_I, FSR_I, FSR_I
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test_end
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test madd_s_precision
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test_op3 madd.s, f0, f1, f2, f0, 0xbf800002, 0x3f800001, 0x3f800001, \
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0x28800000, 0x28800000, 0x28800000, 0x28800000, \
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FSR__, FSR__, FSR__, FSR__
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test_end
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#if DFPU
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test madd_s_nan_dfpu
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/* DFPU madd/msub NaN1, NaN2, NaN3 priority: NaN1, NaN3, NaN2 */
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test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_1, F32_1, \
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F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \
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FSR__, FSR__, FSR__, FSR__
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test_op3 madd.s, f0, f1, f2, f0, F32_1, F32_QNAN(2), F32_1, \
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F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), \
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FSR__, FSR__, FSR__, FSR__
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test_op3 madd.s, f0, f1, f2, f0, F32_1, F32_1, F32_QNAN(3), \
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F32_QNAN(3), F32_QNAN(3), F32_QNAN(3), F32_QNAN(3), \
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FSR__, FSR__, FSR__, FSR__
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test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_QNAN(2), F32_1, \
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F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \
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FSR__, FSR__, FSR__, FSR__
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test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_1, F32_QNAN(3), \
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F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \
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FSR__, FSR__, FSR__, FSR__
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test_op3 madd.s, f0, f1, f2, f0, F32_1, F32_QNAN(2), F32_QNAN(3), \
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F32_QNAN(3), F32_QNAN(3), F32_QNAN(3), F32_QNAN(3), \
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FSR__, FSR__, FSR__, FSR__
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test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_QNAN(2), F32_QNAN(3), \
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F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \
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FSR__, FSR__, FSR__, FSR__
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/* inf * 0 = default NaN */
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test_op3 madd.s, f0, f1, f2, f0, F32_1, F32_PINF, F32_0, \
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F32_DNAN, F32_DNAN, F32_DNAN, F32_DNAN, \
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FSR_V, FSR_V, FSR_V, FSR_V
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/* inf * 0 + SNaN1 = QNaN1 */
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test_op3 madd.s, f0, f1, f2, f0, F32_SNAN(1), F32_PINF, F32_0, \
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F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \
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FSR_V, FSR_V, FSR_V, FSR_V
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/* inf * 0 + QNaN1 = QNaN1 */
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test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_PINF, F32_0, \
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F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \
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FSR_V, FSR_V, FSR_V, FSR_V
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/* madd/msub SNaN turns to QNaN and sets Invalid flag */
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test_op3 madd.s, f0, f1, f2, f0, F32_SNAN(1), F32_1, F32_1, \
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F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \
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FSR_V, FSR_V, FSR_V, FSR_V
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test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_SNAN(2), F32_1, \
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F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \
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FSR_V, FSR_V, FSR_V, FSR_V
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test_end
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#else
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test madd_s_nan_fpu2k
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/* FPU2000 madd/msub NaN1, NaN2, NaN3 priority: NaN2, NaN3, NaN1 */
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test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_1, F32_1, \
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F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \
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FSR__, FSR__, FSR__, FSR__
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test_op3 madd.s, f0, f1, f2, f0, F32_1, F32_QNAN(2), F32_1, \
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F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), \
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FSR__, FSR__, FSR__, FSR__
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test_op3 madd.s, f0, f1, f2, f0, F32_1, F32_1, F32_QNAN(3), \
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F32_QNAN(3), F32_QNAN(3), F32_QNAN(3), F32_QNAN(3), \
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FSR__, FSR__, FSR__, FSR__
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test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_QNAN(2), F32_1, \
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F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), \
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FSR__, FSR__, FSR__, FSR__
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test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_1, F32_QNAN(3), \
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F32_QNAN(3), F32_QNAN(3), F32_QNAN(3), F32_QNAN(3), \
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FSR__, FSR__, FSR__, FSR__
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test_op3 madd.s, f0, f1, f2, f0, F32_1, F32_QNAN(2), F32_QNAN(3), \
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F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), \
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FSR__, FSR__, FSR__, FSR__
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test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_QNAN(2), F32_QNAN(3), \
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F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), \
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FSR__, FSR__, FSR__, FSR__
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/* inf * 0 = default NaN */
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test_op3 madd.s, f0, f1, f2, f0, F32_1, F32_PINF, F32_0, \
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F32_DNAN, F32_DNAN, F32_DNAN, F32_DNAN, \
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FSR__, FSR__, FSR__, FSR__
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/* inf * 0 + SNaN1 = SNaN1 */
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test_op3 madd.s, f0, f1, f2, f0, F32_SNAN(1), F32_PINF, F32_0, \
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F32_SNAN(1), F32_SNAN(1), F32_SNAN(1), F32_SNAN(1), \
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FSR__, FSR__, FSR__, FSR__
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/* inf * 0 + QNaN1 = QNaN1 */
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test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_PINF, F32_0, \
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F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \
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FSR__, FSR__, FSR__, FSR__
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/* madd/msub SNaN is preserved */
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test_op3 madd.s, f0, f1, f2, f0, F32_SNAN(1), F32_1, F32_1, \
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F32_SNAN(1), F32_SNAN(1), F32_SNAN(1), F32_SNAN(1), \
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FSR__, FSR__, FSR__, FSR__
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test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_SNAN(2), F32_1, \
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F32_SNAN(2), F32_SNAN(2), F32_SNAN(2), F32_SNAN(2), \
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FSR__, FSR__, FSR__, FSR__
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test_end
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#endif
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test msub_s
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test_op3 msub.s, f0, f1, f2, f0, 0x3f800000, 0x3f800001, 0x3f800001, \
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0xb4800000, 0xb4800000, 0xb4800000, 0xb4800001, \
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FSR_I, FSR_I, FSR_I, FSR_I
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test_end
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#endif
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test_suite_end
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