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db3be60deb
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
144 lines
3.6 KiB
C
144 lines
3.6 KiB
C
/*
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* QEMU VMWARE paravirtual devices - auxiliary code
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*
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* Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com)
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*
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* Developed by Daynix Computing LTD (http://www.daynix.com)
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*
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* Authors:
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* Dmitry Fleytman <dmitry@daynix.com>
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* Yan Vugenfirer <yan@daynix.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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*/
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#ifndef VMWARE_UTILS_H
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#define VMWARE_UTILS_H
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#include "qemu/range.h"
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#ifndef VMW_SHPRN
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#define VMW_SHPRN(fmt, ...) do {} while (0)
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#endif
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/*
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* Shared memory access functions with byte swap support
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* Each function contains printout for reverse-engineering needs
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*
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*/
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static inline void
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vmw_shmem_read(hwaddr addr, void *buf, int len)
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{
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VMW_SHPRN("SHMEM r: %" PRIx64 ", len: %d to %p", addr, len, buf);
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cpu_physical_memory_read(addr, buf, len);
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}
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static inline void
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vmw_shmem_write(hwaddr addr, void *buf, int len)
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{
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VMW_SHPRN("SHMEM w: %" PRIx64 ", len: %d to %p", addr, len, buf);
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cpu_physical_memory_write(addr, buf, len);
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}
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static inline void
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vmw_shmem_rw(hwaddr addr, void *buf, int len, int is_write)
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{
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VMW_SHPRN("SHMEM r/w: %" PRIx64 ", len: %d (to %p), is write: %d",
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addr, len, buf, is_write);
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cpu_physical_memory_rw(addr, buf, len, is_write);
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}
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static inline void
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vmw_shmem_set(hwaddr addr, uint8 val, int len)
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{
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int i;
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VMW_SHPRN("SHMEM set: %" PRIx64 ", len: %d (value 0x%X)", addr, len, val);
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for (i = 0; i < len; i++) {
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cpu_physical_memory_write(addr + i, &val, 1);
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}
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}
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static inline uint32_t
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vmw_shmem_ld8(hwaddr addr)
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{
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uint8_t res = ldub_phys(&address_space_memory, addr);
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VMW_SHPRN("SHMEM load8: %" PRIx64 " (value 0x%X)", addr, res);
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return res;
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}
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static inline void
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vmw_shmem_st8(hwaddr addr, uint8_t value)
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{
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VMW_SHPRN("SHMEM store8: %" PRIx64 " (value 0x%X)", addr, value);
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stb_phys(&address_space_memory, addr, value);
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}
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static inline uint32_t
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vmw_shmem_ld16(hwaddr addr)
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{
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uint16_t res = lduw_le_phys(&address_space_memory, addr);
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VMW_SHPRN("SHMEM load16: %" PRIx64 " (value 0x%X)", addr, res);
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return res;
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}
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static inline void
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vmw_shmem_st16(hwaddr addr, uint16_t value)
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{
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VMW_SHPRN("SHMEM store16: %" PRIx64 " (value 0x%X)", addr, value);
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stw_le_phys(&address_space_memory, addr, value);
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}
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static inline uint32_t
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vmw_shmem_ld32(hwaddr addr)
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{
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uint32_t res = ldl_le_phys(&address_space_memory, addr);
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VMW_SHPRN("SHMEM load32: %" PRIx64 " (value 0x%X)", addr, res);
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return res;
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}
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static inline void
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vmw_shmem_st32(hwaddr addr, uint32_t value)
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{
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VMW_SHPRN("SHMEM store32: %" PRIx64 " (value 0x%X)", addr, value);
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stl_le_phys(&address_space_memory, addr, value);
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}
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static inline uint64_t
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vmw_shmem_ld64(hwaddr addr)
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{
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uint64_t res = ldq_le_phys(&address_space_memory, addr);
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VMW_SHPRN("SHMEM load64: %" PRIx64 " (value %" PRIx64 ")", addr, res);
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return res;
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}
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static inline void
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vmw_shmem_st64(hwaddr addr, uint64_t value)
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{
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VMW_SHPRN("SHMEM store64: %" PRIx64 " (value %" PRIx64 ")", addr, value);
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stq_le_phys(&address_space_memory, addr, value);
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}
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/* Macros for simplification of operations on array-style registers */
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/*
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* Whether <addr> lies inside of array-style register defined by <base>,
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* number of elements (<cnt>) and element size (<regsize>)
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*
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*/
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#define VMW_IS_MULTIREG_ADDR(addr, base, cnt, regsize) \
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range_covers_byte(base, cnt * regsize, addr)
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/*
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* Returns index of given register (<addr>) in array-style register defined by
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* <base> and element size (<regsize>)
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*
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*/
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#define VMW_MULTIREG_IDX_BY_ADDR(addr, base, regsize) \
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(((addr) - (base)) / (regsize))
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#endif
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