Michael Clark 194eef09d0 RISC-V: Enable second UART on sifive_e and sifive_u ... Previously the second UARTs on the sifive_e and sifive_u machines where disabled due to check-qtest-riscv32 and check-qtest-riscv64 failures. Recent changes in the QEMU core serial code have resolved these failures so the second UARTs can be instantiated. Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>		2018-12-20 12:08:43 -08:00
..
Makefile.objs	RISC-V Build Infrastructure	2018-03-07 08:30:28 +13:00
riscv_hart.c	riscv_hart: Fix crash when introspecting the device	2018-07-19 09:05:48 -07:00
riscv_htif.c	hw: Do not include "exec/address-spaces.h" if it is not necessary	2018-06-01 14:15:10 +02:00
sifive_clint.c	RISC-V: Fix CLINT timecmp low 32-bit writes	2018-12-20 12:08:43 -08:00
sifive_e.c	RISC-V: Enable second UART on sifive_e and sifive_u	2018-12-20 12:08:43 -08:00
sifive_plic.c	RISC-V: Fix PLIC pending bitfield reads	2018-12-20 12:08:43 -08:00
sifive_prci.c	SiFive RISC-V PRCI Block	2018-03-07 08:30:28 +13:00
sifive_test.c	SiFive RISC-V Test Finisher	2018-03-07 08:30:28 +13:00
sifive_u.c	RISC-V: Enable second UART on sifive_e and sifive_u	2018-12-20 12:08:43 -08:00
sifive_uart.c	SiFive RISC-V UART Device	2018-03-07 08:30:28 +13:00
spike.c	riscv: spike: Fix memory leak in the board init	2018-11-08 08:41:06 -08:00
virt.c	hw/riscv/virt: Connect the gpex PCIe	2018-12-20 11:45:20 -08:00