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20d0f9cf6a
The slave mode is not implemented. Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 508dbf2ebe26ec383d3a12a1db5a7890ac8acf20.1441057361.git.jcd@tribudubois.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
88 lines
2.6 KiB
C
88 lines
2.6 KiB
C
/*
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* i.MX I2C Bus Serial Interface registers definition
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*
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* Copyright (C) 2013 Jean-Christophe Dubois. <jcd@tribudubois.net>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#ifndef __IMX_I2C_H_
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#define __IMX_I2C_H_
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#include <hw/sysbus.h>
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#define TYPE_IMX_I2C "imx.i2c"
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#define IMX_I2C(obj) OBJECT_CHECK(IMXI2CState, (obj), TYPE_IMX_I2C)
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#define IMX_I2C_MEM_SIZE 0x14
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/* i.MX I2C memory map */
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#define IADR_ADDR 0x00 /* address register */
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#define IFDR_ADDR 0x04 /* frequency divider register */
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#define I2CR_ADDR 0x08 /* control register */
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#define I2SR_ADDR 0x0c /* status register */
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#define I2DR_ADDR 0x10 /* data register */
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#define IADR_MASK 0xFE
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#define IADR_RESET 0
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#define IFDR_MASK 0x3F
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#define IFDR_RESET 0
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#define I2CR_IEN (1 << 7)
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#define I2CR_IIEN (1 << 6)
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#define I2CR_MSTA (1 << 5)
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#define I2CR_MTX (1 << 4)
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#define I2CR_TXAK (1 << 3)
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#define I2CR_RSTA (1 << 2)
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#define I2CR_MASK 0xFC
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#define I2CR_RESET 0
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#define I2SR_ICF (1 << 7)
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#define I2SR_IAAF (1 << 6)
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#define I2SR_IBB (1 << 5)
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#define I2SR_IAL (1 << 4)
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#define I2SR_SRW (1 << 2)
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#define I2SR_IIF (1 << 1)
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#define I2SR_RXAK (1 << 0)
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#define I2SR_MASK 0xE9
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#define I2SR_RESET 0x81
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#define I2DR_MASK 0xFF
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#define I2DR_RESET 0
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#define ADDR_RESET 0xFF00
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typedef struct IMXI2CState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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MemoryRegion iomem;
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I2CBus *bus;
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qemu_irq irq;
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uint16_t address;
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uint16_t iadr;
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uint16_t ifdr;
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uint16_t i2cr;
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uint16_t i2sr;
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uint16_t i2dr_read;
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uint16_t i2dr_write;
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} IMXI2CState;
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#endif /* __IMX_I2C_H_ */
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