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PLLs are composed of multiple channels. Each channel outputs one clock signal. They are modeled as one device taking the PLL generated clock as input, and outputting a new clock. A channel shares the CM register with its parent PLL, and has its own A2W_CTRL register. A write to the CM register will trigger an update of the PLL and all its channels, while a write to an A2W_CTRL channel register will update the required channel only. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Luc Michel <luc@lmichel.fr> Tested-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
111 lines
2.2 KiB
C
111 lines
2.2 KiB
C
/*
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* BCM2835 CPRMAN clock manager
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*
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* Copyright (c) 2020 Luc Michel <luc@lmichel.fr>
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef HW_MISC_CPRMAN_H
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#define HW_MISC_CPRMAN_H
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#include "hw/sysbus.h"
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#include "hw/qdev-clock.h"
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#define TYPE_BCM2835_CPRMAN "bcm2835-cprman"
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typedef struct BCM2835CprmanState BCM2835CprmanState;
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DECLARE_INSTANCE_CHECKER(BCM2835CprmanState, CPRMAN,
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TYPE_BCM2835_CPRMAN)
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#define CPRMAN_NUM_REGS (0x2000 / sizeof(uint32_t))
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typedef enum CprmanPll {
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CPRMAN_PLLA = 0,
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CPRMAN_PLLC,
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CPRMAN_PLLD,
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CPRMAN_PLLH,
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CPRMAN_PLLB,
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CPRMAN_NUM_PLL
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} CprmanPll;
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typedef enum CprmanPllChannel {
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CPRMAN_PLLA_CHANNEL_DSI0 = 0,
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CPRMAN_PLLA_CHANNEL_CORE,
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CPRMAN_PLLA_CHANNEL_PER,
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CPRMAN_PLLA_CHANNEL_CCP2,
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CPRMAN_PLLC_CHANNEL_CORE2,
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CPRMAN_PLLC_CHANNEL_CORE1,
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CPRMAN_PLLC_CHANNEL_PER,
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CPRMAN_PLLC_CHANNEL_CORE0,
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CPRMAN_PLLD_CHANNEL_DSI0,
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CPRMAN_PLLD_CHANNEL_CORE,
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CPRMAN_PLLD_CHANNEL_PER,
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CPRMAN_PLLD_CHANNEL_DSI1,
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CPRMAN_PLLH_CHANNEL_AUX,
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CPRMAN_PLLH_CHANNEL_RCAL,
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CPRMAN_PLLH_CHANNEL_PIX,
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CPRMAN_PLLB_CHANNEL_ARM,
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CPRMAN_NUM_PLL_CHANNEL,
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} CprmanPllChannel;
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typedef struct CprmanPllState {
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/*< private >*/
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DeviceState parent_obj;
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/*< public >*/
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CprmanPll id;
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uint32_t *reg_cm;
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uint32_t *reg_a2w_ctrl;
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uint32_t *reg_a2w_ana; /* ANA[0] .. ANA[3] */
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uint32_t prediv_mask; /* prediv bit in ana[1] */
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uint32_t *reg_a2w_frac;
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Clock *xosc_in;
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Clock *out;
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} CprmanPllState;
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typedef struct CprmanPllChannelState {
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/*< private >*/
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DeviceState parent_obj;
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/*< public >*/
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CprmanPllChannel id;
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CprmanPll parent;
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uint32_t *reg_cm;
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uint32_t hold_mask;
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uint32_t load_mask;
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uint32_t *reg_a2w_ctrl;
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int fixed_divider;
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Clock *pll_in;
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Clock *out;
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} CprmanPllChannelState;
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struct BCM2835CprmanState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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MemoryRegion iomem;
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CprmanPllState plls[CPRMAN_NUM_PLL];
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CprmanPllChannelState channels[CPRMAN_NUM_PLL_CHANNEL];
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uint32_t regs[CPRMAN_NUM_REGS];
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uint32_t xosc_freq;
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Clock *xosc;
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};
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#endif
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