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This module is specific to the bcm2836 (Pi2). It implements the top level interrupt controller, and mailboxes used for inter-processor synchronisation. Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
52 lines
1.4 KiB
C
52 lines
1.4 KiB
C
/*
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* Raspberry Pi emulation (c) 2012 Gregory Estrade
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* Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous
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*
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* Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft
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* Written by Andrew Baumann
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*
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* This code is licensed under the GNU GPLv2 and later.
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*/
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#ifndef BCM2836_CONTROL_H
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#define BCM2836_CONTROL_H
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#include "hw/sysbus.h"
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/* 4 mailboxes per core, for 16 total */
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#define BCM2836_NCORES 4
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#define BCM2836_MBPERCORE 4
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#define TYPE_BCM2836_CONTROL "bcm2836-control"
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#define BCM2836_CONTROL(obj) \
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OBJECT_CHECK(BCM2836ControlState, (obj), TYPE_BCM2836_CONTROL)
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typedef struct BCM2836ControlState {
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/*< private >*/
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SysBusDevice busdev;
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/*< public >*/
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MemoryRegion iomem;
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/* mailbox state */
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uint32_t mailboxes[BCM2836_NCORES * BCM2836_MBPERCORE];
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/* interrupt routing/control registers */
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uint8_t route_gpu_irq, route_gpu_fiq;
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uint32_t timercontrol[BCM2836_NCORES];
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uint32_t mailboxcontrol[BCM2836_NCORES];
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/* interrupt status regs (derived from input pins; not visible to user) */
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bool gpu_irq, gpu_fiq;
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uint8_t timerirqs[BCM2836_NCORES];
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/* interrupt source registers, post-routing (also input-derived; visible) */
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uint32_t irqsrc[BCM2836_NCORES];
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uint32_t fiqsrc[BCM2836_NCORES];
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/* outputs to CPU cores */
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qemu_irq irq[BCM2836_NCORES];
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qemu_irq fiq[BCM2836_NCORES];
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} BCM2836ControlState;
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#endif
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