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4100d5e6dc
RISC-V machines do not instantiate RISC-V CPUs directly, instead they do that via the hart array. Add a new property for the reset vector address to allow the value to be passed to the CPU, before CPU is realized. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1598924352-89526-3-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
90 lines
2.7 KiB
C
90 lines
2.7 KiB
C
/*
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* QEMU RISCV Hart Array
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*
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* Copyright (c) 2017 SiFive, Inc.
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*
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* Holds the state of a homogeneous array of RISC-V harts
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu/module.h"
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#include "sysemu/reset.h"
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#include "hw/sysbus.h"
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#include "target/riscv/cpu.h"
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#include "hw/qdev-properties.h"
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#include "hw/riscv/riscv_hart.h"
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static Property riscv_harts_props[] = {
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DEFINE_PROP_UINT32("num-harts", RISCVHartArrayState, num_harts, 1),
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DEFINE_PROP_UINT32("hartid-base", RISCVHartArrayState, hartid_base, 0),
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DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type),
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DEFINE_PROP_UINT64("resetvec", RISCVHartArrayState, resetvec,
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DEFAULT_RSTVEC),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void riscv_harts_cpu_reset(void *opaque)
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{
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RISCVCPU *cpu = opaque;
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cpu_reset(CPU(cpu));
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}
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static bool riscv_hart_realize(RISCVHartArrayState *s, int idx,
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char *cpu_type, Error **errp)
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{
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object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx], cpu_type);
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qdev_prop_set_uint64(DEVICE(&s->harts[idx]), "resetvec", s->resetvec);
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s->harts[idx].env.mhartid = s->hartid_base + idx;
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qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]);
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return qdev_realize(DEVICE(&s->harts[idx]), NULL, errp);
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}
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static void riscv_harts_realize(DeviceState *dev, Error **errp)
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{
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RISCVHartArrayState *s = RISCV_HART_ARRAY(dev);
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int n;
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s->harts = g_new0(RISCVCPU, s->num_harts);
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for (n = 0; n < s->num_harts; n++) {
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if (!riscv_hart_realize(s, n, s->cpu_type, errp)) {
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return;
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}
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}
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}
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static void riscv_harts_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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device_class_set_props(dc, riscv_harts_props);
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dc->realize = riscv_harts_realize;
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}
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static const TypeInfo riscv_harts_info = {
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.name = TYPE_RISCV_HART_ARRAY,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(RISCVHartArrayState),
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.class_init = riscv_harts_class_init,
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};
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static void riscv_harts_register_types(void)
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{
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type_register_static(&riscv_harts_info);
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}
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type_init(riscv_harts_register_types)
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