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8d5f07fa3b
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1098 c046a42c-6fe2-441c-8c8c-71466251a162
114 lines
4.6 KiB
C
114 lines
4.6 KiB
C
/*
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* QEMU Sun4m System Emulator
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h"
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#include "m48t08.h"
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#define KERNEL_LOAD_ADDR 0x00004000
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#define MMU_CONTEXT_TBL 0x00003000
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#define MMU_L1PTP (MMU_CONTEXT_TBL + 0x0400)
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#define MMU_L2PTP (MMU_CONTEXT_TBL + 0x0800)
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#define PROM_ADDR 0xffd04000
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#define PROM_FILENAMEB "proll.bin"
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#define PROM_FILENAMEE "proll.elf"
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#define PROLL_MAGIC_ADDR 0x20000000
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#define PHYS_JJ_EEPROM 0x71200000 /* [2000] MK48T08 */
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#define PHYS_JJ_IDPROM_OFF 0x1FD8
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#define PHYS_JJ_EEPROM_SIZE 0x2000
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#define PHYS_JJ_IOMMU 0x10000000 /* First page of sun4m IOMMU */
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#define PHYS_JJ_TCX_FB 0x50800000 /* Start address, frame buffer body */
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#define PHYS_JJ_TCX_0E 0x5E000000 /* Top address, one byte used. */
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#define PHYS_JJ_IOMMU 0x10000000 /* First page of sun4m IOMMU */
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#define PHYS_JJ_LEDMA 0x78400010 /* ledma, off by 10 from unused SCSI */
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#define PHYS_JJ_LE 0x78C00000 /* LANCE, typical sun4m */
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#define PHYS_JJ_LE_IRQ 6
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#define PHYS_JJ_CLOCK 0x71D00000
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#define PHYS_JJ_CLOCK_IRQ 10
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#define PHYS_JJ_CLOCK1 0x71D10000
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#define PHYS_JJ_CLOCK1_IRQ 14
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#define PHYS_JJ_INTR0 0x71E00000 /* CPU0 interrupt control registers */
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#define PHYS_JJ_INTR_G 0x71E10000 /* Master interrupt control registers */
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/* TSC handling */
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uint64_t cpu_get_tsc()
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{
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return qemu_get_clock(vm_clock);
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}
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void DMA_run() {}
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void SB16_run() {}
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int serial_can_receive(SerialState *s) { return 0; }
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void serial_receive_byte(SerialState *s, int ch) {}
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void serial_receive_break(SerialState *s) {}
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static m48t08_t *nvram;
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/* Sun4m hardware initialisation */
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void sun4m_init(int ram_size, int vga_ram_size, int boot_device,
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DisplayState *ds, const char **fd_filename, int snapshot,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename)
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{
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char buf[1024];
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int ret, linux_boot;
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unsigned long bios_offset;
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linux_boot = (kernel_filename != NULL);
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/* allocate RAM */
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cpu_register_physical_memory(0, ram_size, 0);
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bios_offset = ram_size;
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iommu_init(PHYS_JJ_IOMMU);
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sched_init(PHYS_JJ_INTR0, PHYS_JJ_INTR_G);
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tcx_init(ds, PHYS_JJ_TCX_FB);
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lance_init(&nd_table[0], PHYS_JJ_LE_IRQ, PHYS_JJ_LE, PHYS_JJ_LEDMA);
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nvram = m48t08_init(PHYS_JJ_EEPROM, PHYS_JJ_EEPROM_SIZE, &nd_table[0].macaddr);
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timer_init(PHYS_JJ_CLOCK, PHYS_JJ_CLOCK_IRQ);
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timer_init(PHYS_JJ_CLOCK1, PHYS_JJ_CLOCK1_IRQ);
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magic_init(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR, PROLL_MAGIC_ADDR);
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/* We load Proll as the kernel and start it. It will issue a magic
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IO to load the real kernel */
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if (linux_boot) {
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snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAMEB);
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ret = load_kernel(buf,
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phys_ram_base + KERNEL_LOAD_ADDR);
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if (ret < 0) {
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fprintf(stderr, "qemu: could not load kernel '%s'\n",
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buf);
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exit(1);
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}
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}
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/* Setup a MMU entry for entire address space */
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stl_raw(phys_ram_base + MMU_CONTEXT_TBL, (MMU_L1PTP >> 4) | 1);
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stl_raw(phys_ram_base + MMU_L1PTP, (MMU_L2PTP >> 4) | 1);
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stl_raw(phys_ram_base + MMU_L1PTP + (0x01 << 2), (MMU_L2PTP >> 4) | 1); // 01.. == 00..
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stl_raw(phys_ram_base + MMU_L1PTP + (0xff << 2), (MMU_L2PTP >> 4) | 1); // ff.. == 00..
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stl_raw(phys_ram_base + MMU_L1PTP + (0xf0 << 2), (MMU_L2PTP >> 4) | 1); // f0.. == 00..
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/* 3 = U:RWX S:RWX */
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stl_raw(phys_ram_base + MMU_L2PTP, (3 << PTE_ACCESS_SHIFT) | 2);
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stl_raw(phys_ram_base + MMU_L2PTP, ((0x01 << PTE_PPN_SHIFT) >> 4 ) | (3 << PTE_ACCESS_SHIFT) | 2);
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}
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