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65a67f0fe5
Having the callee add 1 to shift amount is misleading (see the NM_LSA case in decode_nanomips_32_48_opc() where we have to manually substract 1). Rather have the callers pass a modified $sa. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241112172022.88348-4-philmd@linaro.org>
54 lines
1.3 KiB
C
54 lines
1.3 KiB
C
/*
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* Address Computation and Large Constant Instructions
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*
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* Copyright (c) 2004-2005 Jocelyn Mayer
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* Copyright (c) 2006 Marius Groeger (FPU operations)
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* Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
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* Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support)
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* Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support)
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* Copyright (c) 2020 Philippe Mathieu-Daudé
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*
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* SPDX-License-Identifier: LGPL-2.1-or-later
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*/
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#include "qemu/osdep.h"
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#include "translate.h"
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bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, int sa)
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{
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TCGv t0;
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TCGv t1;
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if (rd == 0) {
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/* Treat as NOP. */
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return true;
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}
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t0 = tcg_temp_new();
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t1 = tcg_temp_new();
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gen_load_gpr(t0, rs);
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gen_load_gpr(t1, rt);
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tcg_gen_shli_tl(t0, t0, sa);
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tcg_gen_add_tl(cpu_gpr[rd], t0, t1);
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tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
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return true;
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}
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bool gen_dlsa(DisasContext *ctx, int rd, int rt, int rs, int sa)
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{
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TCGv t0;
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TCGv t1;
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check_mips_64(ctx);
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if (rd == 0) {
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/* Treat as NOP. */
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return true;
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}
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t0 = tcg_temp_new();
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t1 = tcg_temp_new();
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gen_load_gpr(t0, rs);
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gen_load_gpr(t1, rt);
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tcg_gen_shli_tl(t0, t0, sa);
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tcg_gen_add_tl(cpu_gpr[rd], t0, t1);
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return true;
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}
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