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714bae7351
Implement the phys (aka hard) VP push. PowerVM uses this operation. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Michael Kowal <kowal@linux.ibm.com> Tested-by: Gautam Menghani <gautam@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-49-npiggin@gmail.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
158 lines
6.3 KiB
C
158 lines
6.3 KiB
C
/*
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* QEMU PowerPC XIVE2 interrupt controller model (POWER10)
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*
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* Copyright (c) 2019-2024, IBM Corporation.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef PPC_XIVE2_H
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#define PPC_XIVE2_H
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#include "hw/ppc/xive.h"
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#include "hw/ppc/xive2_regs.h"
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#include "hw/sysbus.h"
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/*
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* XIVE2 Router (POWER10)
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*/
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typedef struct Xive2Router {
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SysBusDevice parent;
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XiveFabric *xfb;
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} Xive2Router;
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#define TYPE_XIVE2_ROUTER "xive2-router"
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OBJECT_DECLARE_TYPE(Xive2Router, Xive2RouterClass, XIVE2_ROUTER);
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/*
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* Configuration flags
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*/
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#define XIVE2_GEN1_TIMA_OS 0x00000001
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#define XIVE2_VP_SAVE_RESTORE 0x00000002
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#define XIVE2_THREADID_8BITS 0x00000004
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#define XIVE2_EN_VP_GRP_PRIORITY 0x00000008
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#define XIVE2_VP_INT_PRIO 0x00000030
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typedef struct Xive2RouterClass {
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SysBusDeviceClass parent;
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/* XIVE table accessors */
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int (*get_eas)(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx,
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Xive2Eas *eas);
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int (*get_pq)(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx,
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uint8_t *pq);
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int (*set_pq)(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx,
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uint8_t *pq);
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int (*get_end)(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx,
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Xive2End *end);
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int (*write_end)(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx,
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Xive2End *end, uint8_t word_number);
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int (*get_nvp)(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx,
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Xive2Nvp *nvp);
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int (*write_nvp)(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx,
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Xive2Nvp *nvp, uint8_t word_number);
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int (*get_nvgc)(Xive2Router *xrtr, bool crowd,
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uint8_t nvgc_blk, uint32_t nvgc_idx,
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Xive2Nvgc *nvgc);
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int (*write_nvgc)(Xive2Router *xrtr, bool crowd,
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uint8_t nvgc_blk, uint32_t nvgc_idx,
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Xive2Nvgc *nvgc);
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uint8_t (*get_block_id)(Xive2Router *xrtr);
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uint32_t (*get_config)(Xive2Router *xrtr);
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} Xive2RouterClass;
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int xive2_router_get_eas(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx,
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Xive2Eas *eas);
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int xive2_router_get_end(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx,
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Xive2End *end);
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int xive2_router_write_end(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx,
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Xive2End *end, uint8_t word_number);
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int xive2_router_get_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx,
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Xive2Nvp *nvp);
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int xive2_router_write_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx,
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Xive2Nvp *nvp, uint8_t word_number);
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int xive2_router_get_nvgc(Xive2Router *xrtr, bool crowd,
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uint8_t nvgc_blk, uint32_t nvgc_idx,
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Xive2Nvgc *nvgc);
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int xive2_router_write_nvgc(Xive2Router *xrtr, bool crowd,
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uint8_t nvgc_blk, uint32_t nvgc_idx,
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Xive2Nvgc *nvgc);
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uint32_t xive2_router_get_config(Xive2Router *xrtr);
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void xive2_router_notify(XiveNotifier *xn, uint32_t lisn, bool pq_checked);
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void xive2_notify(Xive2Router *xrtr, uint32_t lisn, bool pq_checked);
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/*
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* XIVE2 Presenter (POWER10)
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*/
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int xive2_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx,
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uint8_t format,
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uint8_t nvt_blk, uint32_t nvt_idx,
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bool crowd, bool cam_ignore,
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uint32_t logic_serv);
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uint64_t xive2_presenter_nvp_backlog_op(XivePresenter *xptr,
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uint8_t blk, uint32_t idx,
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uint16_t offset);
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uint64_t xive2_presenter_nvgc_backlog_op(XivePresenter *xptr,
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bool crowd,
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uint8_t blk, uint32_t idx,
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uint16_t offset, uint16_t val);
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/*
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* XIVE2 END ESBs (POWER10)
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*/
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#define TYPE_XIVE2_END_SOURCE "xive2-end-source"
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OBJECT_DECLARE_SIMPLE_TYPE(Xive2EndSource, XIVE2_END_SOURCE)
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typedef struct Xive2EndSource {
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DeviceState parent;
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uint32_t nr_ends;
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/* ESB memory region */
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uint32_t esb_shift;
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MemoryRegion esb_mmio;
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Xive2Router *xrtr;
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} Xive2EndSource;
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/*
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* XIVE2 Thread Interrupt Management Area (POWER10)
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*/
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void xive2_tm_set_hv_cppr(XivePresenter *xptr, XiveTCTX *tctx,
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hwaddr offset, uint64_t value, unsigned size);
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void xive2_tm_set_os_cppr(XivePresenter *xptr, XiveTCTX *tctx,
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hwaddr offset, uint64_t value, unsigned size);
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void xive2_tm_set_os_pending(XivePresenter *xptr, XiveTCTX *tctx,
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hwaddr offset, uint64_t value, unsigned size);
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void xive2_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
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uint64_t value, unsigned size);
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uint64_t xive2_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,
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hwaddr offset, unsigned size);
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void xive2_tm_pull_os_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx,
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hwaddr offset, uint64_t value, unsigned size);
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bool xive2_tm_irq_precluded(XiveTCTX *tctx, int ring, uint8_t priority);
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void xive2_tm_set_lsmfb(XiveTCTX *tctx, int ring, uint8_t priority);
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void xive2_tm_set_hv_target(XivePresenter *xptr, XiveTCTX *tctx,
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hwaddr offset, uint64_t value, unsigned size);
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void xive2_tm_push_pool_ctx(XivePresenter *xptr, XiveTCTX *tctx,
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hwaddr offset, uint64_t value, unsigned size);
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uint64_t xive2_tm_pull_pool_ctx(XivePresenter *xptr, XiveTCTX *tctx,
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hwaddr offset, unsigned size);
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void xive2_tm_push_phys_ctx(XivePresenter *xptr, XiveTCTX *tctx,
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hwaddr offset, uint64_t value, unsigned size);
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uint64_t xive2_tm_pull_phys_ctx(XivePresenter *xptr, XiveTCTX *tctx,
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hwaddr offset, unsigned size);
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void xive2_tm_pull_phys_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx,
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hwaddr offset, uint64_t value, unsigned size);
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void xive2_tm_ack_os_el(XivePresenter *xptr, XiveTCTX *tctx,
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hwaddr offset, uint64_t value, unsigned size);
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#endif /* PPC_XIVE2_H */
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