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4b3a1eb066
This commit adds AES to max78000_soc Signed-off-by: Jackson Donaldson <jcksn@duck.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20250704223239.248781-12-jcksn@duck.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
51 lines
1.1 KiB
C
51 lines
1.1 KiB
C
/*
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* MAX78000 SOC
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*
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* Copyright (c) 2025 Jackson Donaldson <jcksn@duck.com>
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef HW_ARM_MAX78000_SOC_H
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#define HW_ARM_MAX78000_SOC_H
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#include "hw/or-irq.h"
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#include "hw/arm/armv7m.h"
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#include "hw/misc/max78000_aes.h"
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#include "hw/misc/max78000_gcr.h"
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#include "hw/misc/max78000_icc.h"
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#include "hw/char/max78000_uart.h"
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#include "hw/misc/max78000_trng.h"
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#include "qom/object.h"
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#define TYPE_MAX78000_SOC "max78000-soc"
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OBJECT_DECLARE_SIMPLE_TYPE(MAX78000State, MAX78000_SOC)
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#define FLASH_BASE_ADDRESS 0x10000000
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#define FLASH_SIZE (512 * 1024)
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#define SRAM_BASE_ADDRESS 0x20000000
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#define SRAM_SIZE (128 * 1024)
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/* The MAX78k has 2 instruction caches; only icc0 matters, icc1 is for RISC */
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#define MAX78000_NUM_ICC 2
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#define MAX78000_NUM_UART 3
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struct MAX78000State {
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SysBusDevice parent_obj;
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ARMv7MState armv7m;
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MemoryRegion sram;
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MemoryRegion flash;
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Max78000GcrState gcr;
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Max78000IccState icc[MAX78000_NUM_ICC];
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Max78000UartState uart[MAX78000_NUM_UART];
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Max78000TrngState trng;
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Max78000AesState aes;
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Clock *sysclk;
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};
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#endif
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