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069852d159
This commit implements the True Random Number Generator for the MAX78000 Signed-off-by: Jackson Donaldson <jcksn@duck.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20250704223239.248781-9-jcksn@duck.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
140 lines
3.7 KiB
C
140 lines
3.7 KiB
C
/*
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* MAX78000 True Random Number Generator
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*
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* Copyright (c) 2025 Jackson Donaldson <jcksn@duck.com>
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "trace.h"
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#include "hw/irq.h"
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#include "migration/vmstate.h"
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#include "hw/misc/max78000_trng.h"
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#include "qemu/guest-random.h"
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static uint64_t max78000_trng_read(void *opaque, hwaddr addr,
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unsigned int size)
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{
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uint32_t data;
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Max78000TrngState *s = opaque;
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switch (addr) {
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case CTRL:
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return s->ctrl;
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case STATUS:
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return 1;
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case DATA:
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/*
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* When interrupts are enabled, reading random data should cause a
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* new interrupt to be generated; since there's always a random number
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* available, we could qemu_set_irq(s->irq, s->ctrl & RND_IE). Because
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* of how trng_write is set up, this is always a noop, so don't
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*/
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qemu_guest_getrandom_nofail(&data, sizeof(data));
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return data;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%"
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HWADDR_PRIx "\n", __func__, addr);
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break;
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}
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return 0;
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}
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static void max78000_trng_write(void *opaque, hwaddr addr,
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uint64_t val64, unsigned int size)
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{
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Max78000TrngState *s = opaque;
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uint32_t val = val64;
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switch (addr) {
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case CTRL:
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/* TODO: implement AES keygen */
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s->ctrl = val;
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/*
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* This device models random number generation as taking 0 time.
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* A new random number is always available, so the condition for the
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* RND interrupt is always fulfilled; we can just set irq to 1.
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*/
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if (val & RND_IE) {
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qemu_set_irq(s->irq, 1);
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} else{
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qemu_set_irq(s->irq, 0);
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}
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%"
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HWADDR_PRIx "\n", __func__, addr);
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break;
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}
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}
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static void max78000_trng_reset_hold(Object *obj, ResetType type)
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{
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Max78000TrngState *s = MAX78000_TRNG(obj);
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s->ctrl = 0;
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s->status = 0;
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s->data = 0;
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}
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static const MemoryRegionOps max78000_trng_ops = {
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.read = max78000_trng_read,
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.write = max78000_trng_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid.min_access_size = 4,
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.valid.max_access_size = 4,
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};
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static const VMStateDescription max78000_trng_vmstate = {
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.name = TYPE_MAX78000_TRNG,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (const VMStateField[]) {
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VMSTATE_UINT32(ctrl, Max78000TrngState),
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VMSTATE_UINT32(status, Max78000TrngState),
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VMSTATE_UINT32(data, Max78000TrngState),
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VMSTATE_END_OF_LIST()
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}
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};
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static void max78000_trng_init(Object *obj)
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{
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Max78000TrngState *s = MAX78000_TRNG(obj);
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sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
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memory_region_init_io(&s->mmio, obj, &max78000_trng_ops, s,
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TYPE_MAX78000_TRNG, 0x1000);
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sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
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}
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static void max78000_trng_class_init(ObjectClass *klass, const void *data)
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{
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ResettableClass *rc = RESETTABLE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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rc->phases.hold = max78000_trng_reset_hold;
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dc->vmsd = &max78000_trng_vmstate;
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}
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static const TypeInfo max78000_trng_info = {
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.name = TYPE_MAX78000_TRNG,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(Max78000TrngState),
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.instance_init = max78000_trng_init,
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.class_init = max78000_trng_class_init,
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};
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static void max78000_trng_register_types(void)
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{
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type_register_static(&max78000_trng_info);
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}
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type_init(max78000_trng_register_types)
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