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3ec680e64c
This commit implements the Instruction Cache Controller for the MAX78000 Signed-off-by: Jackson Donaldson <jcksn@duck.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20250704223239.248781-3-jcksn@duck.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
121 lines
2.9 KiB
C
121 lines
2.9 KiB
C
/*
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* MAX78000 Instruction Cache
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*
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* Copyright (c) 2025 Jackson Donaldson <jcksn@duck.com>
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "trace.h"
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#include "hw/irq.h"
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#include "migration/vmstate.h"
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#include "hw/misc/max78000_icc.h"
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static uint64_t max78000_icc_read(void *opaque, hwaddr addr,
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unsigned int size)
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{
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Max78000IccState *s = opaque;
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switch (addr) {
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case ICC_INFO:
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return s->info;
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case ICC_SZ:
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return s->sz;
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case ICC_CTRL:
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return s->ctrl;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Bad offset 0x%" HWADDR_PRIx "\n",
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__func__, addr);
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return 0;
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}
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}
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static void max78000_icc_write(void *opaque, hwaddr addr,
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uint64_t val64, unsigned int size)
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{
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Max78000IccState *s = opaque;
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switch (addr) {
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case ICC_CTRL:
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s->ctrl = 0x10000 | (val64 & 1);
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break;
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case ICC_INVALIDATE:
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Bad offset 0x%" HWADDR_PRIx "\n",
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__func__, addr);
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break;
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}
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}
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static const MemoryRegionOps max78000_icc_ops = {
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.read = max78000_icc_read,
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.write = max78000_icc_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid.min_access_size = 4,
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.valid.max_access_size = 4,
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};
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static const VMStateDescription max78000_icc_vmstate = {
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.name = TYPE_MAX78000_ICC,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (const VMStateField[]) {
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VMSTATE_UINT32(info, Max78000IccState),
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VMSTATE_UINT32(sz, Max78000IccState),
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VMSTATE_UINT32(ctrl, Max78000IccState),
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VMSTATE_END_OF_LIST()
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}
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};
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static void max78000_icc_reset_hold(Object *obj, ResetType type)
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{
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Max78000IccState *s = MAX78000_ICC(obj);
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s->info = 0;
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s->sz = 0x10000010;
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s->ctrl = 0x10000;
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}
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static void max78000_icc_init(Object *obj)
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{
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Max78000IccState *s = MAX78000_ICC(obj);
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memory_region_init_io(&s->mmio, obj, &max78000_icc_ops, s,
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TYPE_MAX78000_ICC, 0x800);
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sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
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}
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static void max78000_icc_class_init(ObjectClass *klass, const void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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ResettableClass *rc = RESETTABLE_CLASS(klass);
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rc->phases.hold = max78000_icc_reset_hold;
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dc->vmsd = &max78000_icc_vmstate;
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}
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static const TypeInfo max78000_icc_info = {
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.name = TYPE_MAX78000_ICC,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(Max78000IccState),
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.instance_init = max78000_icc_init,
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.class_init = max78000_icc_class_init,
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};
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static void max78000_icc_register_types(void)
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{
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type_register_static(&max78000_icc_info);
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}
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type_init(max78000_icc_register_types)
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