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33dfff7e34
This commit implements AES for the MAX78000 Signed-off-by: Jackson Donaldson <jcksn@duck.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20250704223239.248781-11-jcksn@duck.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
352 lines
9.0 KiB
C
352 lines
9.0 KiB
C
/*
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* MAX78000 Global Control Registers
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*
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* Copyright (c) 2025 Jackson Donaldson <jcksn@duck.com>
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "trace.h"
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#include "hw/irq.h"
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#include "system/runstate.h"
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#include "migration/vmstate.h"
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#include "hw/qdev-properties.h"
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#include "hw/char/max78000_uart.h"
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#include "hw/misc/max78000_trng.h"
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#include "hw/misc/max78000_aes.h"
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#include "hw/misc/max78000_gcr.h"
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static void max78000_gcr_reset_hold(Object *obj, ResetType type)
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{
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DeviceState *dev = DEVICE(obj);
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Max78000GcrState *s = MAX78000_GCR(dev);
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s->sysctrl = 0x21002;
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s->rst0 = 0;
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/* All clocks are always ready */
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s->clkctrl = 0x3e140008;
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s->pm = 0x3f000;
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s->pclkdiv = 0;
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s->pclkdis0 = 0xffffffff;
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s->memctrl = 0x5;
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s->memz = 0;
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s->sysst = 0;
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s->rst1 = 0;
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s->pckdis1 = 0xffffffff;
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s->eventen = 0;
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s->revision = 0xa1;
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s->sysie = 0;
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s->eccerr = 0;
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s->ecced = 0;
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s->eccie = 0;
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s->eccaddr = 0;
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}
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static uint64_t max78000_gcr_read(void *opaque, hwaddr addr,
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unsigned int size)
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{
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Max78000GcrState *s = opaque;
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switch (addr) {
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case SYSCTRL:
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return s->sysctrl;
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case RST0:
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return s->rst0;
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case CLKCTRL:
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return s->clkctrl;
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case PM:
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return s->pm;
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case PCLKDIV:
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return s->pclkdiv;
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case PCLKDIS0:
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return s->pclkdis0;
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case MEMCTRL:
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return s->memctrl;
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case MEMZ:
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return s->memz;
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case SYSST:
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return s->sysst;
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case RST1:
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return s->rst1;
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case PCKDIS1:
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return s->pckdis1;
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case EVENTEN:
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return s->eventen;
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case REVISION:
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return s->revision;
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case SYSIE:
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return s->sysie;
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case ECCERR:
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return s->eccerr;
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case ECCED:
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return s->ecced;
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case ECCIE:
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return s->eccie;
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case ECCADDR:
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return s->eccaddr;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%"
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HWADDR_PRIx "\n", __func__, addr);
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return 0;
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}
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}
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static void max78000_gcr_write(void *opaque, hwaddr addr,
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uint64_t val64, unsigned int size)
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{
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Max78000GcrState *s = opaque;
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uint32_t val = val64;
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uint8_t zero[0xc000] = {0};
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switch (addr) {
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case SYSCTRL:
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/* Checksum calculations always pass immediately */
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s->sysctrl = (val & 0x30000) | 0x1002;
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break;
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case RST0:
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if (val & SYSTEM_RESET) {
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qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
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}
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if (val & PERIPHERAL_RESET) {
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/*
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* Peripheral reset resets all peripherals. The CPU
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* retains its state. The GPIO, watchdog timers, AoD,
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* RAM retention, and general control registers (GCR),
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* including the clock configuration, are unaffected.
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*/
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val = UART2_RESET | UART1_RESET | UART0_RESET |
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ADC_RESET | CNN_RESET | TRNG_RESET |
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RTC_RESET | I2C0_RESET | SPI1_RESET |
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TMR3_RESET | TMR2_RESET | TMR1_RESET |
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TMR0_RESET | WDT0_RESET | DMA_RESET;
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}
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if (val & SOFT_RESET) {
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/* Soft reset also resets GPIO */
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val = UART2_RESET | UART1_RESET | UART0_RESET |
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ADC_RESET | CNN_RESET | TRNG_RESET |
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RTC_RESET | I2C0_RESET | SPI1_RESET |
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TMR3_RESET | TMR2_RESET | TMR1_RESET |
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TMR0_RESET | GPIO1_RESET | GPIO0_RESET |
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DMA_RESET;
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}
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if (val & UART2_RESET) {
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device_cold_reset(s->uart2);
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}
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if (val & UART1_RESET) {
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device_cold_reset(s->uart1);
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}
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if (val & UART0_RESET) {
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device_cold_reset(s->uart0);
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}
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if (val & TRNG_RESET) {
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device_cold_reset(s->trng);
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}
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if (val & AES_RESET) {
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device_cold_reset(s->aes);
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}
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/* TODO: As other devices are implemented, add them here */
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break;
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case CLKCTRL:
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s->clkctrl = val | SYSCLK_RDY;
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break;
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case PM:
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s->pm = val;
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break;
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case PCLKDIV:
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s->pclkdiv = val;
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break;
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case PCLKDIS0:
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s->pclkdis0 = val;
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break;
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case MEMCTRL:
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s->memctrl = val;
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break;
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case MEMZ:
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if (val & ram0) {
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address_space_write(&s->sram_as, SYSRAM0_START,
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MEMTXATTRS_UNSPECIFIED, zero, 0x8000);
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}
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if (val & ram1) {
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address_space_write(&s->sram_as, SYSRAM1_START,
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MEMTXATTRS_UNSPECIFIED, zero, 0x8000);
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}
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if (val & ram2) {
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address_space_write(&s->sram_as, SYSRAM2_START,
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MEMTXATTRS_UNSPECIFIED, zero, 0xC000);
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}
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if (val & ram3) {
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address_space_write(&s->sram_as, SYSRAM3_START,
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MEMTXATTRS_UNSPECIFIED, zero, 0x4000);
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}
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break;
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case SYSST:
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s->sysst = val;
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break;
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case RST1:
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/* TODO: As other devices are implemented, add them here */
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s->rst1 = val;
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break;
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case PCKDIS1:
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s->pckdis1 = val;
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break;
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case EVENTEN:
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s->eventen = val;
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break;
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case REVISION:
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s->revision = val;
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break;
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case SYSIE:
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s->sysie = val;
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break;
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case ECCERR:
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s->eccerr = val;
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break;
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case ECCED:
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s->ecced = val;
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break;
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case ECCIE:
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s->eccie = val;
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break;
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case ECCADDR:
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s->eccaddr = val;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
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__func__, addr);
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break;
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}
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}
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static const Property max78000_gcr_properties[] = {
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DEFINE_PROP_LINK("sram", Max78000GcrState, sram,
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TYPE_MEMORY_REGION, MemoryRegion*),
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DEFINE_PROP_LINK("uart0", Max78000GcrState, uart0,
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TYPE_MAX78000_UART, DeviceState*),
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DEFINE_PROP_LINK("uart1", Max78000GcrState, uart1,
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TYPE_MAX78000_UART, DeviceState*),
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DEFINE_PROP_LINK("uart2", Max78000GcrState, uart2,
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TYPE_MAX78000_UART, DeviceState*),
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DEFINE_PROP_LINK("trng", Max78000GcrState, trng,
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TYPE_MAX78000_TRNG, DeviceState*),
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DEFINE_PROP_LINK("aes", Max78000GcrState, aes,
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TYPE_MAX78000_AES, DeviceState*),
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};
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static const MemoryRegionOps max78000_gcr_ops = {
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.read = max78000_gcr_read,
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.write = max78000_gcr_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid.min_access_size = 4,
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.valid.max_access_size = 4,
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};
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static const VMStateDescription vmstate_max78000_gcr = {
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.name = TYPE_MAX78000_GCR,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (const VMStateField[]) {
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VMSTATE_UINT32(sysctrl, Max78000GcrState),
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VMSTATE_UINT32(rst0, Max78000GcrState),
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VMSTATE_UINT32(clkctrl, Max78000GcrState),
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VMSTATE_UINT32(pm, Max78000GcrState),
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VMSTATE_UINT32(pclkdiv, Max78000GcrState),
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VMSTATE_UINT32(pclkdis0, Max78000GcrState),
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VMSTATE_UINT32(memctrl, Max78000GcrState),
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VMSTATE_UINT32(memz, Max78000GcrState),
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VMSTATE_UINT32(sysst, Max78000GcrState),
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VMSTATE_UINT32(rst1, Max78000GcrState),
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VMSTATE_UINT32(pckdis1, Max78000GcrState),
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VMSTATE_UINT32(eventen, Max78000GcrState),
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VMSTATE_UINT32(revision, Max78000GcrState),
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VMSTATE_UINT32(sysie, Max78000GcrState),
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VMSTATE_UINT32(eccerr, Max78000GcrState),
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VMSTATE_UINT32(ecced, Max78000GcrState),
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VMSTATE_UINT32(eccie, Max78000GcrState),
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VMSTATE_UINT32(eccaddr, Max78000GcrState),
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VMSTATE_END_OF_LIST()
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}
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};
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static void max78000_gcr_init(Object *obj)
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{
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Max78000GcrState *s = MAX78000_GCR(obj);
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memory_region_init_io(&s->mmio, obj, &max78000_gcr_ops, s,
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TYPE_MAX78000_GCR, 0x400);
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sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
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}
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static void max78000_gcr_realize(DeviceState *dev, Error **errp)
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{
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Max78000GcrState *s = MAX78000_GCR(dev);
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address_space_init(&s->sram_as, s->sram, "sram");
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}
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static void max78000_gcr_class_init(ObjectClass *klass, const void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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ResettableClass *rc = RESETTABLE_CLASS(klass);
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device_class_set_props(dc, max78000_gcr_properties);
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dc->realize = max78000_gcr_realize;
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dc->vmsd = &vmstate_max78000_gcr;
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rc->phases.hold = max78000_gcr_reset_hold;
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}
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static const TypeInfo max78000_gcr_info = {
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.name = TYPE_MAX78000_GCR,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(Max78000GcrState),
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.instance_init = max78000_gcr_init,
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.class_init = max78000_gcr_class_init,
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};
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static void max78000_gcr_register_types(void)
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{
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type_register_static(&max78000_gcr_info);
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}
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type_init(max78000_gcr_register_types)
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