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Coverity Scan noted an unusual pattern in the MAX78000 aes device, with duplicated calls to set_decrypt. This commit adds a comment noting why the implementation is correct. Signed-off-by: Jackson Donaldson <jcksn@duck.com> Message-id: 20250716002622.84685-1-jcksn@duck.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
230 lines
6.0 KiB
C
230 lines
6.0 KiB
C
/*
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* MAX78000 AES
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*
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* Copyright (c) 2025 Jackson Donaldson <jcksn@duck.com>
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "trace.h"
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#include "hw/irq.h"
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#include "migration/vmstate.h"
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#include "hw/misc/max78000_aes.h"
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#include "crypto/aes.h"
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static void max78000_aes_set_status(Max78000AesState *s)
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{
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s->status = 0;
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if (s->result_index >= 16) {
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s->status |= OUTPUT_FULL;
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}
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if (s->result_index == 0) {
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s->status |= OUTPUT_EMPTY;
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}
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if (s->data_index >= 16) {
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s->status |= INPUT_FULL;
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}
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if (s->data_index == 0) {
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s->status |= INPUT_EMPTY;
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}
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}
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static uint64_t max78000_aes_read(void *opaque, hwaddr addr,
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unsigned int size)
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{
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Max78000AesState *s = opaque;
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switch (addr) {
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case CTRL:
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return s->ctrl;
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case STATUS:
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return s->status;
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case INTFL:
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return s->intfl;
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case INTEN:
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return s->inten;
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case FIFO:
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if (s->result_index >= 4) {
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s->intfl &= ~DONE;
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s->result_index -= 4;
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max78000_aes_set_status(s);
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return ldl_be_p(&s->result[s->result_index]);
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} else{
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return 0;
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}
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%"
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HWADDR_PRIx "\n", __func__, addr);
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break;
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}
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return 0;
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}
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static void max78000_aes_do_crypto(Max78000AesState *s)
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{
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int keylen = 256;
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uint8_t *keydata = s->key;
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if ((s->ctrl & KEY_SIZE) == 0) {
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keylen = 128;
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keydata += 16;
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} else if ((s->ctrl & KEY_SIZE) == 1 << 6) {
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keylen = 192;
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keydata += 8;
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}
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/*
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* The MAX78000 AES engine stores an internal key, which it uses only
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* for decryption. This results in the slighly odd looking pairs of
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* set_encrypt and set_decrypt calls below; s->internal_key is
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* being stored for later use in both cases.
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*/
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AES_KEY key;
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if ((s->ctrl & TYPE) == 0) {
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AES_set_encrypt_key(keydata, keylen, &key);
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AES_set_decrypt_key(keydata, keylen, &s->internal_key);
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AES_encrypt(s->data, s->result, &key);
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s->result_index = 16;
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} else if ((s->ctrl & TYPE) == 1 << 8) {
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AES_set_decrypt_key(keydata, keylen, &key);
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AES_set_decrypt_key(keydata, keylen, &s->internal_key);
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AES_decrypt(s->data, s->result, &key);
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s->result_index = 16;
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} else{
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AES_decrypt(s->data, s->result, &s->internal_key);
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s->result_index = 16;
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}
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s->intfl |= DONE;
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}
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static void max78000_aes_write(void *opaque, hwaddr addr,
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uint64_t val64, unsigned int size)
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{
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Max78000AesState *s = opaque;
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uint32_t val = val64;
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switch (addr) {
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case CTRL:
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if (val & OUTPUT_FLUSH) {
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s->result_index = 0;
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val &= ~OUTPUT_FLUSH;
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}
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if (val & INPUT_FLUSH) {
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s->data_index = 0;
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val &= ~INPUT_FLUSH;
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}
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if (val & START) {
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max78000_aes_do_crypto(s);
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}
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/* Hardware appears to stay enabled even if 0 written */
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s->ctrl = val | (s->ctrl & AES_EN);
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break;
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case FIFO:
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assert(s->data_index <= 12);
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stl_be_p(&s->data[12 - s->data_index], val);
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s->data_index += 4;
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if (s->data_index >= 16) {
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s->data_index = 0;
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max78000_aes_do_crypto(s);
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}
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break;
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case KEY_BASE ... KEY_END - 4:
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stl_be_p(&s->key[(KEY_END - KEY_BASE - 4) - (addr - KEY_BASE)], val);
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%"
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HWADDR_PRIx "\n", __func__, addr);
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break;
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}
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max78000_aes_set_status(s);
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}
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static void max78000_aes_reset_hold(Object *obj, ResetType type)
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{
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Max78000AesState *s = MAX78000_AES(obj);
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s->ctrl = 0;
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s->status = 0;
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s->intfl = 0;
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s->inten = 0;
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s->data_index = 0;
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s->result_index = 0;
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memset(s->data, 0, sizeof(s->data));
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memset(s->key, 0, sizeof(s->key));
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memset(s->result, 0, sizeof(s->result));
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memset(&s->internal_key, 0, sizeof(s->internal_key));
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}
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static const MemoryRegionOps max78000_aes_ops = {
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.read = max78000_aes_read,
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.write = max78000_aes_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid.min_access_size = 4,
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.valid.max_access_size = 4,
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};
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static const VMStateDescription vmstate_max78000_aes = {
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.name = TYPE_MAX78000_AES,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (const VMStateField[]) {
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VMSTATE_UINT32(ctrl, Max78000AesState),
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VMSTATE_UINT32(status, Max78000AesState),
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VMSTATE_UINT32(intfl, Max78000AesState),
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VMSTATE_UINT32(inten, Max78000AesState),
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VMSTATE_UINT8_ARRAY(data, Max78000AesState, 16),
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VMSTATE_UINT8_ARRAY(key, Max78000AesState, 32),
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VMSTATE_UINT8_ARRAY(result, Max78000AesState, 16),
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VMSTATE_UINT32_ARRAY(internal_key.rd_key, Max78000AesState, 60),
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VMSTATE_INT32(internal_key.rounds, Max78000AesState),
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VMSTATE_END_OF_LIST()
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}
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};
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static void max78000_aes_init(Object *obj)
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{
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Max78000AesState *s = MAX78000_AES(obj);
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sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
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memory_region_init_io(&s->mmio, obj, &max78000_aes_ops, s,
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TYPE_MAX78000_AES, 0xc00);
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sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
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}
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static void max78000_aes_class_init(ObjectClass *klass, const void *data)
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{
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ResettableClass *rc = RESETTABLE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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rc->phases.hold = max78000_aes_reset_hold;
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dc->vmsd = &vmstate_max78000_aes;
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}
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static const TypeInfo max78000_aes_info = {
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.name = TYPE_MAX78000_AES,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(Max78000AesState),
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.instance_init = max78000_aes_init,
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.class_init = max78000_aes_class_init,
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};
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static void max78000_aes_register_types(void)
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{
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type_register_static(&max78000_aes_info);
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}
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type_init(max78000_aes_register_types)
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