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a10b9d93ec
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3 Commits

Author SHA1 Message Date
Keith Packard
a10b9d93ec riscv: Add semihosting support 
Adapt the arm semihosting support code for RISCV. This implementation
is based on the standard for RISC-V semihosting version 0.2 as
documented in

   https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2

Signed-off-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20210107170717.2098982-6-keithp@keithp.com>
Message-Id: <20210108224256.2321-17-alex.bennee@linaro.org>
 2021-01-18 10:05:06 +00:00
Paolo Bonzini
a9a7490786 default-configs: use TARGET_ARCH key 
Replace the individual TARGET_*=y lines with TARGET_ARCH,
similar to how TARGET_BASE_ARCH is handled already.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
 2020-10-03 08:18:57 -04:00
Paolo Bonzini
fdb75aeff7 configure: remove target configuration 
The config-target.mak files are small constant, we can therefore just
write them down explicitly.

This removes a pretty large part of the configure script, including the
whole logic to detect which accelerators are supported by each target.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
 2020-10-03 08:18:56 -04:00