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target/arm: Add support for MTE to SCTLR_ELx
This does not attempt to rectify all of the res0 bits, but does clear the mte bits when not enabled. Since there is no high-part mapping of SCTLR, aa32 mode cannot write to these bits. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200626033144.790098-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -4698,6 +4698,22 @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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{
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{
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ARMCPU *cpu = env_archcpu(env);
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ARMCPU *cpu = env_archcpu(env);
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if (arm_feature(env, ARM_FEATURE_PMSA) && !cpu->has_mpu) {
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/* M bit is RAZ/WI for PMSA with no MPU implemented */
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value &= ~SCTLR_M;
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}
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/* ??? Lots of these bits are not implemented. */
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if (ri->state == ARM_CP_STATE_AA64 && !cpu_isar_feature(aa64_mte, cpu)) {
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if (ri->opc1 == 6) { /* SCTLR_EL3 */
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value &= ~(SCTLR_ITFSB | SCTLR_TCF | SCTLR_ATA);
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} else {
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value &= ~(SCTLR_ITFSB | SCTLR_TCF0 | SCTLR_TCF |
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SCTLR_ATA0 | SCTLR_ATA);
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}
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}
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if (raw_read(env, ri) == value) {
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if (raw_read(env, ri) == value) {
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/* Skip the TLB flush if nothing actually changed; Linux likes
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/* Skip the TLB flush if nothing actually changed; Linux likes
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* to do a lot of pointless SCTLR writes.
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* to do a lot of pointless SCTLR writes.
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@ -4705,13 +4721,8 @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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return;
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return;
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}
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}
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if (arm_feature(env, ARM_FEATURE_PMSA) && !cpu->has_mpu) {
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/* M bit is RAZ/WI for PMSA with no MPU implemented */
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value &= ~SCTLR_M;
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}
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raw_write(env, ri, value);
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raw_write(env, ri, value);
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/* ??? Lots of these bits are not implemented. */
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/* This may enable/disable the MMU, so do a TLB flush. */
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/* This may enable/disable the MMU, so do a TLB flush. */
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tlb_flush(CPU(cpu));
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tlb_flush(CPU(cpu));
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