mirror of
https://github.com/qemu/qemu.git
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do not generate MP table if one CPU (no APIC in QEMU in this case) - added wbinvd (ignored in QEMU but useful on real hardware)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2191 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard
parent
47d02f6d5c
commit
e3e97e7c90
BIN
pc-bios/bios.bin
BIN
pc-bios/bios.bin
Binary file not shown.
@ -1,83 +1,10 @@
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Index: BIOS-bochs-latest
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===================================================================
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RCS file: /cvsroot/bochs/bochs/bios/BIOS-bochs-latest,v
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retrieving revision 1.133
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diff -u -w -r1.133 BIOS-bochs-latest
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Binary files /tmp/cvsrjjP5I and BIOS-bochs-latest differ
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Index: rombios.c
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===================================================================
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RCS file: /cvsroot/bochs/bochs/bios/rombios.c,v
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retrieving revision 1.170
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diff -u -w -r1.170 rombios.c
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--- rombios.c 30 Sep 2006 11:22:53 -0000 1.170
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+++ rombios.c 1 Oct 2006 16:03:53 -0000
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@@ -4115,7 +4115,7 @@
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case 3:
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set_e820_range(ES, regs.u.r16.di,
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0x00100000L,
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- extended_memory_size - 0x10000L, 1);
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+ extended_memory_size - ACPI_DATA_SIZE, 1);
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regs.u.r32.ebx = 4;
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regs.u.r32.eax = 0x534D4150;
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regs.u.r32.ecx = 0x14;
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@@ -4124,7 +4124,7 @@
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break;
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case 4:
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set_e820_range(ES, regs.u.r16.di,
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- extended_memory_size - 0x10000L,
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+ extended_memory_size - ACPI_DATA_SIZE,
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extended_memory_size, 3); // ACPI RAM
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regs.u.r32.ebx = 5;
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regs.u.r32.eax = 0x534D4150;
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@@ -8723,7 +8723,7 @@
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.align 16
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bios32_entry_point:
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- pushf
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+ pushfd
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cmp eax, #0x49435024 ;; "$PCI"
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jne unknown_service
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mov eax, #0x80000000
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@@ -8750,12 +8750,12 @@
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#ifdef BX_QEMU
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and dword ptr[esp+8],0xfffffffc ;; reset CS.RPL for kqemu
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#endif
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- popf
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+ popfd
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retf
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.align 16
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pcibios_protected:
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- pushf
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+ pushfd
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cli
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push esi
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push edi
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@@ -8864,7 +8864,7 @@
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#ifdef BX_QEMU
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and dword ptr[esp+8],0xfffffffc ;; reset CS.RPL for kqemu
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#endif
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- popf
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+ popfd
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stc
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retf
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pci_pro_ok:
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@@ -8874,7 +8874,7 @@
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#ifdef BX_QEMU
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and dword ptr[esp+8],0xfffffffc ;; reset CS.RPL for kqemu
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#endif
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- popf
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+ popfd
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clc
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retf
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Index: rombios.h
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Index: rombios.h
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===================================================================
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===================================================================
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RCS file: /cvsroot/bochs/bochs/bios/rombios.h,v
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RCS file: /cvsroot/bochs/bochs/bios/rombios.h,v
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retrieving revision 1.1
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retrieving revision 1.2
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diff -u -w -r1.1 rombios.h
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diff -u -w -r1.2 rombios.h
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--- rombios.h 30 Sep 2006 11:22:53 -0000 1.1
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--- rombios.h 1 Oct 2006 16:39:18 -0000 1.2
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+++ rombios.h 1 Oct 2006 16:03:54 -0000
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+++ rombios.h 2 Oct 2006 18:31:41 -0000
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@@ -19,7 +19,7 @@
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@@ -19,7 +19,7 @@
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// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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@ -87,132 +14,56 @@ diff -u -w -r1.1 rombios.h
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#define BX_ROMBIOS32 1
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#define BX_ROMBIOS32 1
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#define DEBUG_ROMBIOS 0
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#define DEBUG_ROMBIOS 0
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@@ -48,3 +48,7 @@
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#endif
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#define BX_INFO(format, p...) bios_printf(BIOS_PRINTF_INFO, format, ##p)
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#define BX_PANIC(format, p...) bios_printf(BIOS_PRINTF_DEBHALT, format, ##p)
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+
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+#define ACPI_DATA_SIZE 0x00010000L
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+#define PM_IO_BASE 0xb000
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+#define CPU_COUNT_ADDR 0xf000
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Index: rombios32.c
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Index: rombios32.c
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===================================================================
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===================================================================
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RCS file: /cvsroot/bochs/bochs/bios/rombios32.c,v
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RCS file: /cvsroot/bochs/bochs/bios/rombios32.c,v
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retrieving revision 1.4
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retrieving revision 1.6
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diff -u -w -r1.4 rombios32.c
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diff -u -w -r1.6 rombios32.c
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--- rombios32.c 30 Sep 2006 11:22:53 -0000 1.4
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--- rombios32.c 2 Oct 2006 06:29:37 -0000 1.6
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+++ rombios32.c 1 Oct 2006 16:03:54 -0000
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+++ rombios32.c 2 Oct 2006 18:31:41 -0000
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@@ -55,13 +55,10 @@
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@@ -45,6 +45,8 @@
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: "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) \
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: "0" (index))
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#define APIC_ENABLED 0x0100
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+#define wbinvd() asm volatile("wbinvd")
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-#define CPU_COUNT_ADDR 0xf000
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#define AP_BOOT_ADDR 0x10000
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#define MPTABLE_MAX_SIZE 0x00002000
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-#define ACPI_DATA_SIZE 0x00010000
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#define SMI_CMD_IO_ADDR 0xb2
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-#define PM_IO_BASE 0xb000
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#define BIOS_TMP_STORAGE 0x00030000 /* 64 KB used to copy the BIOS to shadow RAM */
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@@ -354,12 +351,14 @@
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void delay_ms(int n)
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{
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- int i, j, r1, r2;
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+ int i, j;
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for(i = 0; i < n; i++) {
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-#if BX_QEMU
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+#ifdef BX_QEMU
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/* approximative ! */
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for(j = 0; j < 1000000; j++);
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#else
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+ {
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+ int r1, r2;
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j = 66;
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r1 = inb(0x61) & 0x10;
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do {
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@@ -369,6 +368,7 @@
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r1 = r2;
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}
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} while (j > 0);
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+ }
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#endif
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}
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}
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Index: rombios32start.S
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===================================================================
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RCS file: /cvsroot/bochs/bochs/bios/rombios32start.S,v
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retrieving revision 1.1
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diff -u -w -r1.1 rombios32start.S
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--- rombios32start.S 28 Sep 2006 18:56:20 -0000 1.1
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+++ rombios32start.S 1 Oct 2006 16:03:54 -0000
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@@ -1,3 +1,25 @@
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+/////////////////////////////////////////////////////////////////////////
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+// $Id: bios.diff,v 1.15 2006-10-01 16:08:15 bellard Exp $
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+/////////////////////////////////////////////////////////////////////////
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+//
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+// 32 bit Bochs BIOS init code
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+// Copyright (C) 2006 Fabrice Bellard
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+//
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+// This library is free software; you can redistribute it and/or
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+// modify it under the terms of the GNU Lesser General Public
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+// License as published by the Free Software Foundation; either
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+// version 2 of the License, or (at your option) any later version.
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+//
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+// This library is distributed in the hope that it will be useful,
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+// but WITHOUT ANY WARRANTY; without even the implied warranty of
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+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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+// Lesser General Public License for more details.
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+//
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+// You should have received a copy of the GNU Lesser General Public
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+// License along with this library; if not, write to the Free Software
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+// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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+#include "rombios.h"
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+
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+
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.globl _start
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#define CPUID_APIC (1 << 9)
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.globl smp_ap_boot_code_start
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.globl smp_ap_boot_code_end
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@@ -6,8 +28,6 @@
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.global smm_code_start
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.global smm_code_end
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-#define PM_IO_BASE 0xb000
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#define APIC_BASE ((uint8_t *)0xfee00000)
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-
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@@ -591,6 +593,7 @@
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_start:
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PCIDevice *d = &i440_pcidev;
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/* clear bss section */
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int v;
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xor %eax, %eax
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@@ -18,13 +38,11 @@
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jmp rombios32_init
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+ wbinvd();
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v = pci_config_readb(d, 0x59);
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v = (v & 0x0f) | (0x10);
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pci_config_writeb(d, 0x59, v);
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@@ -645,7 +648,7 @@
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outb(0xb3, 0x01);
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-#define CPU_COUNT 0xf000
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/* raise an SMI interrupt */
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-
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- outb(0xb2, 0x01);
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.code16
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+ outb(0xb2, 0x00);
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smp_ap_boot_code_start:
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xor %ax, %ax
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mov %ax, %ds
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- incw CPU_COUNT
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+ incw CPU_COUNT_ADDR
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1:
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hlt
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jmp 1b
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@@ -33,7 +51,7 @@
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/* code to relocate SMBASE to 0xa0000 */
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smm_relocation_start:
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mov $0x38000 + 0x7efc, %ebx
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- mov (%ebx), %al /* revision ID to see if x86_64 or x86 */
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+ addr32 mov (%ebx), %al /* revision ID to see if x86_64 or x86 */
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cmp $0x64, %al
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je 1f
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mov $0x38000 + 0x7ef8, %ebx
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@@ -42,7 +60,7 @@
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mov $0x38000 + 0x7f00, %ebx
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2:
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movl $0xa0000, %eax
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- movl %eax, (%ebx)
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+ addr32 movl %eax, (%ebx)
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rsm
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smm_relocation_end:
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/* wait until SMM code executed */
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while (inb(0xb3) != 0x00);
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@@ -656,6 +659,7 @@
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/* copy the SMM code */
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memcpy((void *)0xa8000, &smm_code_start,
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&smm_code_end - &smm_code_start);
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+ wbinvd();
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/* close the SMM memory window and enable normal SMM */
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pci_config_writeb(&i440_pcidev, 0x72, 0x02 | 0x08);
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@@ -848,6 +852,11 @@
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int ioapic_id, i, len;
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int mp_config_table_size;
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+#ifdef BX_QEMU
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+ if (smp_cpus <= 1)
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+ return;
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+#endif
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+
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#ifdef BX_USE_EBDA_TABLES
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mp_config_table = (uint8_t *)(ram_size - ACPI_DATA_SIZE - MPTABLE_MAX_SIZE);
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#else
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