Proxmox-Port/qemu
1
0
Fork 0
mirror of https://github.com/qemu/qemu.git synced 2025-08-09 10:25:06 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

tcg-sparc: Implement movcond.

Browse Source 
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Richard Henderson 2012-10-10 09:02:37 -07:00 committed by Blue Swirl
parent 24c7f75459
commit ded37f0d96
2 changed files with 38 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

43
tcg/sparc/tcg-target.c
View File

@ -539,6 +539,22 @@ static void tcg_out_brcond_i32(TCGContext *s, TCGCond cond,
tcg_out_nop(s); tcg_out_nop(s);
} }
static void tcg_out_movcc(TCGContext *s, TCGCond cond, int cc, TCGArg ret,
TCGArg v1, int v1const)
{
tcg_out32(s, ARITH_MOVCC | cc | INSN_RD(ret)
| INSN_RS1(tcg_cond_to_bcond[cond])
| (v1const ? INSN_IMM11(v1) : INSN_RS2(v1)));
}
static void tcg_out_movcond_i32(TCGContext *s, TCGCond cond, TCGArg ret,
TCGArg c1, TCGArg c2, int c2const,
TCGArg v1, int v1const)
{
tcg_out_cmp(s, c1, c2, c2const);
tcg_out_movcc(s, cond, MOVCC_ICC, ret, v1, v1const);
}
#if TCG_TARGET_REG_BITS == 64 #if TCG_TARGET_REG_BITS == 64
static void tcg_out_brcond_i64(TCGContext *s, TCGCond cond, static void tcg_out_brcond_i64(TCGContext *s, TCGCond cond,
TCGArg arg1, TCGArg arg2, int const_arg2, TCGArg arg1, TCGArg arg2, int const_arg2,
@ -548,6 +564,14 @@ static void tcg_out_brcond_i64(TCGContext *s, TCGCond cond,
tcg_out_branch_i64(s, tcg_cond_to_bcond[cond], label_index); tcg_out_branch_i64(s, tcg_cond_to_bcond[cond], label_index);
tcg_out_nop(s); tcg_out_nop(s);
} }
static void tcg_out_movcond_i64(TCGContext *s, TCGCond cond, TCGArg ret,
TCGArg c1, TCGArg c2, int c2const,
TCGArg v1, int v1const)
{
tcg_out_cmp(s, c1, c2, c2const);
tcg_out_movcc(s, cond, MOVCC_XCC, ret, v1, v1const);
}
#else #else
static void tcg_out_brcond2_i32(TCGContext *s, TCGCond cond, static void tcg_out_brcond2_i32(TCGContext *s, TCGCond cond,
TCGArg al, TCGArg ah, TCGArg al, TCGArg ah,
@ -621,9 +645,7 @@ static void tcg_out_setcond_i32(TCGContext *s, TCGCond cond, TCGArg ret,
default: default:
tcg_out_cmp(s, c1, c2, c2const); tcg_out_cmp(s, c1, c2, c2const);
tcg_out_movi_imm13(s, ret, 0); tcg_out_movi_imm13(s, ret, 0);
tcg_out32(s, ARITH_MOVCC | INSN_RD(ret) tcg_out_movcc(s, cond, MOVCC_ICC, ret, 1, 1);
| INSN_RS1(tcg_cond_to_bcond[cond])
| MOVCC_ICC | INSN_IMM11(1));
return; return;
} }
@ -641,9 +663,7 @@ static void tcg_out_setcond_i64(TCGContext *s, TCGCond cond, TCGArg ret,
{ {
tcg_out_cmp(s, c1, c2, c2const); tcg_out_cmp(s, c1, c2, c2const);
tcg_out_movi_imm13(s, ret, 0); tcg_out_movi_imm13(s, ret, 0);
tcg_out32 (s, ARITH_MOVCC | INSN_RD(ret) tcg_out_movcc(s, cond, MOVCC_XCC, ret, 1, 1);
| INSN_RS1(tcg_cond_to_bcond[cond])
| MOVCC_XCC | INSN_IMM11(1));
} }
#else #else
static void tcg_out_setcond2_i32(TCGContext *s, TCGCond cond, TCGArg ret, static void tcg_out_setcond2_i32(TCGContext *s, TCGCond cond, TCGArg ret,
@ -1202,6 +1222,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
tcg_out_setcond_i32(s, args[3], args[0], args[1], tcg_out_setcond_i32(s, args[3], args[0], args[1],
args[2], const_args[2]); args[2], const_args[2]);
break; break;
case INDEX_op_movcond_i32:
tcg_out_movcond_i32(s, args[5], args[0], args[1],
args[2], const_args[2], args[3], const_args[3]);
break;
#if TCG_TARGET_REG_BITS == 32 #if TCG_TARGET_REG_BITS == 32
case INDEX_op_brcond2_i32: case INDEX_op_brcond2_i32:
@ -1337,7 +1361,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
tcg_out_setcond_i64(s, args[3], args[0], args[1], tcg_out_setcond_i64(s, args[3], args[0], args[1],
args[2], const_args[2]); args[2], const_args[2]);
break; break;
case INDEX_op_movcond_i64:
tcg_out_movcond_i64(s, args[5], args[0], args[1],
args[2], const_args[2], args[3], const_args[3]);
break;
#endif #endif
gen_arith: gen_arith:
tcg_out_arithc(s, args[0], args[1], args[2], const_args[2], c); tcg_out_arithc(s, args[0], args[1], args[2], const_args[2], c);
@ -1392,6 +1419,7 @@ static const TCGTargetOpDef sparc_op_defs[] = {
{ INDEX_op_brcond_i32, { "r", "rJ" } }, { INDEX_op_brcond_i32, { "r", "rJ" } },
{ INDEX_op_setcond_i32, { "r", "r", "rJ" } }, { INDEX_op_setcond_i32, { "r", "r", "rJ" } },
{ INDEX_op_movcond_i32, { "r", "r", "rJ", "rI", "0" } },
#if TCG_TARGET_REG_BITS == 32 #if TCG_TARGET_REG_BITS == 32
{ INDEX_op_brcond2_i32, { "r", "r", "rJ", "rJ" } }, { INDEX_op_brcond2_i32, { "r", "r", "rJ", "rJ" } },
@ -1441,6 +1469,7 @@ static const TCGTargetOpDef sparc_op_defs[] = {
{ INDEX_op_brcond_i64, { "r", "rJ" } }, { INDEX_op_brcond_i64, { "r", "rJ" } },
{ INDEX_op_setcond_i64, { "r", "r", "rJ" } }, { INDEX_op_setcond_i64, { "r", "r", "rJ" } },
{ INDEX_op_movcond_i64, { "r", "r", "rJ", "rI", "0" } },
#endif #endif
#if TCG_TARGET_REG_BITS == 64 #if TCG_TARGET_REG_BITS == 64

4
tcg/sparc/tcg-target.h
View File

@ -99,7 +99,7 @@ typedef enum {
#define TCG_TARGET_HAS_nand_i32 0 #define TCG_TARGET_HAS_nand_i32 0
#define TCG_TARGET_HAS_nor_i32 0 #define TCG_TARGET_HAS_nor_i32 0
#define TCG_TARGET_HAS_deposit_i32 0 #define TCG_TARGET_HAS_deposit_i32 0
#define TCG_TARGET_HAS_movcond_i32 0 #define TCG_TARGET_HAS_movcond_i32 1
#if TCG_TARGET_REG_BITS == 64 #if TCG_TARGET_REG_BITS == 64
#define TCG_TARGET_HAS_div_i64 1 #define TCG_TARGET_HAS_div_i64 1
@ -121,7 +121,7 @@ typedef enum {
#define TCG_TARGET_HAS_nand_i64 0 #define TCG_TARGET_HAS_nand_i64 0
#define TCG_TARGET_HAS_nor_i64 0 #define TCG_TARGET_HAS_nor_i64 0
#define TCG_TARGET_HAS_deposit_i64 0 #define TCG_TARGET_HAS_deposit_i64 0
#define TCG_TARGET_HAS_movcond_i64 0 #define TCG_TARGET_HAS_movcond_i64 1
#endif #endif
#define TCG_TARGET_HAS_GUEST_BASE #define TCG_TARGET_HAS_GUEST_BASE